This tutorial presents an overview of the technological advances in millimeter-wave (mm-wave) circuit components, antennas, and propagation that will soon allow 60-GHz transceivers to provide multigigabit per second (multi-Gb/s) wireless communication data transfers in the consumer marketplace. Our goal is to help engineers understand the convergence of communications, circuits, and antennas, as the emerging world of subterahertz and terahertz wireless communications will require understanding at the intersections of these areas. This paper covers trends and recent accomplishments in a wide range of circuits and systems topics that must be understood to create massively broadband wireless communication systems of the future. In this paper, we present some evolving applications of massively broadband wireless communications, and use tables and graphs to show research progress from the literature on various radio system components, including on-chip and in-package antennas, radio-frequency (RF) power amplifiers (PAs), low-noise amplifiers (LNAs), voltage-controlled oscillators (VCOs), mixers, and analog-to-digital converters (ADCs). We focus primarily on silicon-based technologies, as these provide the best means of implementing very low-cost, highly integrated 60-GHz mm-wave circuits. In addition, the paper illuminates characterization techniques that are required to competently design and fabricate mm-wave devices in silicon, and illustrates effects of the 60-GHz RF propagation channel for both in-building and outdoor use. The paper concludes with an overview of the standardization and commercialization efforts for 60-GHz multi-Gb/s devices, and presents a novel way to compare the data rate versus power efficiency for future broadband devices.

http://faculty.poly.edu/~tsr/wp-content/uploads/publications/abstract17.pdf

State of the Art in 60-GHz Integrated Circuits and Systems for Wireless Communications

This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

Distributed communications systems providing and supporting radio frequency (RF) communication services and digital data services, and related components and methods are disclosed. The RF communication services can be distributed over optical fiber to client devices, such as remote units for example. Power can also be distributed over electrical medium that is provided to distribute digital data services, if desired, to provide power to remote communications devices and/or client devices coupled to the remote communications devices for operation. In this manner, as an example, the same electrical medium used to transport digital data signals in the distributed antenna system can also be employed to provide power to the remote communications devices and/or client devices coupled to the remote communications devices. Power may be injected and switched from two or more power sources over selected electrical medium to distribute power for power-consuming components supporting RF communications services and digital data services.

Providing digital data services as electrical signals and radio-frequency (RF) communications over optical fiber in distributed communications systems, and related components and methods

Progress in 40Gb/s optical dual- polarization (DP) QPSK systems inspired an idea of 100G transmission by optical frequency division multiplexing (FDM) of QPSK-modulated channels [1]. A practical solution suggests two 58Gb/s DP QPSK channels, spaced by 50GHz (Fig. 21.7.1). The challenge is in implementing a 6b ADC operating at sampling rate of 29Gs/s, as compared to 24Gs/s reported before [2]. The other challenge is reduction of ADC sampling jitter. In an interleaved architecture, jitter is limited by the timing mismatch between the clocks of T&H circuits. While initial timing error is compensated during ADC calibration, its spread over the input frequency range and drift may still impact jitter performance. This paper presents, to our knowledge for the first time, a 6b ADC operating up to 40Gs/s with power dissipation ≪ 1.5W. The 30% margin for the sampling rate reduces interleaved timing errors and therefore sampling jitter below 0.25ps-rms. The ADC also includes on-chip test signal synthesizer that generates a gigahertz range sinusoidal signal to simplify production testing.

A 40GS/s 6b ADC in 65nm CMOS

This paper presents two ultra-high-speed SerDes dedicated for PAM4 and NRZ data The PAM4 TX incorporates an output driver with 3-tap FFE and adjustable weighting to deliver clean outputs at 4 levels, and the PAM4 RX employs a purely linear full-rate CDR and CTLE/1-tap DFE combination to recover and demultiplex the data NRZ TX includes a tree-structure MUX with built-in PLL and phase aligner NRZ RX adopts linear PD with special vernier technique to handle the 56 Gb/s input data All chips have been verified in silicon with reasonable performance, providing prospective design examples for next-generation 400 GbE

Design of 56 Gb/s NRZ and PAM4 SerDes Transceivers in CMOS Technologies

This paper presents the design of an analog-front-end (AFE) integrated into a DSP-based transceiver for both serial 10 Gbps KR-backplane and long-reach-multimode-fiber (LRM) applications. The receiver consists of a programmable gain amplifier (PGA) and a 6-bit 4-way time-interleaved ADC, which is digitally calibrated to compensate for the offset, gain and phase mismatches between the interleaved channels. With a 5 GHz input signal, the ADC achieves overall SNDR of 29 dB, while the measured SNDR of flash sub-ADC is 31.6 dB. The power efficiency FoM of the complete interleaved ADC is 1.4 pJ per conversion step. The PLL uses a calibrated LC-VCO and the TX features a full-rate 3-tap de-emphasis at the output. Inductively tuned buffers connected in tandem are employed to distribute the 10 GHz clock. Random and deterministic jitter measured at the TX output are 0.38 psrms and 2.65 pspp, respectively. Implemented in 65 nm CMOS technology, the AFE occupies an area of 3 mm2 and consumes 500 mW from a 1 V supply. BER of less than 10-15 is measured over legacy backplanes with 26 dB loss at Nyquist and the measured transceiver optical sensitivity is less than -13 dBm for all four LRM stressors, exceeding both the KR and the LRM specifications.

A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber

The demand for bandwidth has fueled the deployment of 10Gb/s traffic over legacy data links such as serial backplanes (10GBase-KR) and multimode fiber (10GBase-MMF) which were originally intended for much lower data rates [1,2]. Under severe channel impairments, a DSP-based transceiver provides robust performance and enables power/area scaling with processes [3–5]. This work describes a 65nm CMOS AFE integrated in a DSP-based PHY for 10Gb/s KR/MMF applications.

21.7 A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s Serial links over backplane and multimode fiber

A 39.8-44.6 Gb/s transmitter and receiver chipset designed in 40 nm CMOS is presented. The line-side TX implements a 2-tap FIR filter with delay-based pre-emphasis. The line-side RX uses a quarter-rate CDR architecture. The TX output shows 0.9 pspp ISI and 0.2 psrms RJ at 0.87 W. The RX achieves a jitter tolerance of 0.6 UIpp at 100 MHz and an input sensitivity of 20 mV pp\mathchar"702D diff at 1.05 W. The combined transmitter/receiver equalization enables 44.6 Gb/s data transmission using 231-1 PRBS at BER 10-12 over a channel with >21 dB loss at Nyquist frequency.

A Sub-2 W 39.8–44.6 Gb/s Transmitter and Receiver Chipset With SFI-5.2 Interface in 40 nm CMOS

An 8.5-11.5-Gbps SONET transceiver with referenceless clock and data recovery (CDR) employing an algorithmic frequency acquisition scheme is presented. Without any training sequence, the frequency acquisition algorithm utilizes a modified digital quadricorrelator frequency detector (M-DQFD) incorporated into an LC-based VCO coarse tuning adjustment. M-DQFD eliminates the dead-zone problem associated with high dispersion and low SNR links. Fabricated in 65-nm CMOS process, the transceiver complies with stringent OC-192 jitter requirements. With a 400- μs acquisition time, the receiver achieves a high-frequency jitter tolerance of 0.58UIpp at 10-mVppd input sensitivity. The transmitter output exhibits a random jitter of 205fsrms. The transceiver occupies 0.97 mm2 and consumes 125 mA at 1.0-V supply voltage.

An 8.5–11.5-Gbps SONET Transceiver With Referenceless Frequency Acquisition

At data rates beyond 10Gb/s, most wireline links employ NRZ signaling. Serial NRZ links as high as 56Gb/s and 60Gb/s have been reported [1]. Nevertheless, as the rate increases, the constraints imposed by the channel, package, and die become more severe and do not benefit from process scaling in the same fashion that circuit design does. Reflections from impedance discontinuities in the PCB and package caused by vias and connectors introduce significant signal loss and distortions at higher frequencies. Even with an ideal channel, at every package-die interface, there is an intrinsic parasitic capacitance due to the pads and the ESD circuit amounting to at least 150fF, and a 50Ω resistor termination at both the transmit and receive ends resulting in an intrinsic pole at 23GHz or lower. In light of all these limitations, serial NRZ signaling beyond 60Gb/s appears suboptimal in terms of both power and performance. Utilizing various modulation techniques such as PAM4, one can achieve a higher spectral efficiency [2]. To enable such transmission formats, high-speed moderate-resolution data converters are required. This paper describes a 36Gb/s transmitter based on an 18GS/s 8b DAC implemented in 28nm CMOS, compliant to the new IEEE802.3bj standard for 100G Ethernet over backplane and copper cables [3].

Ullas Singh

Papers

A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber

21.7 A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s Serial links over backplane and multimode fiber

A Sub-2 W 39.8–44.6 Gb/s Transmitter and Receiver Chipset With SFI-5.2 Interface in 40 nm CMOS

An 8.5–11.5-Gbps SONET Transceiver With Referenceless Frequency Acquisition

3.4 A 36Gb/s PAM4 transmitter using an 8b 18GS/S DAC in 28nm CMOS