A
Anand Vasani
Researcher at Broadcom
Publications - 13
Citations - 267
Anand Vasani is an academic researcher from Broadcom. The author has contributed to research in topics: CMOS & Chipset. The author has an hindex of 8, co-authored 13 publications receiving 255 citations.
Papers
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Journal ArticleDOI
A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber
Jun Cao,Bo Zhang,Ullas Singh,Delong Cui,Anand Vasani,Adesh Garg,Wei Zhang,Namik Kocaman,Deyi Pi,Bharath Raghavan,Hui Pan,Ichiro Fujimori,Afshin Momtaz +12 more
TL;DR: An analog-front-end (AFE) integrated into a DSP-based transceiver for both serial 10 Gbps KR-backplane and long-reach-multimode-fiber applications, exceeding both the KR and the LRM specifications.
Proceedings ArticleDOI
21.7 A 500mW digitally calibrated AFE in 65nm CMOS for 10Gb/s Serial links over backplane and multimode fiber
Jun Cao,Bo Zhang,Ullas Singh,Delong Cui,Anand Vasani,Adesh Garg,Wei Zhang,Namik Kocaman,Deyi Pi,Bharath Raghavan,Hui Pan,Ichiro Fujimori,Afshin Momtaz +12 more
TL;DR: This work describes a 65nm CMOS AFE integrated in a DSP-based PHY for 10Gb/s KR/MMF applications.
Journal ArticleDOI
A Sub-2 W 39.8–44.6 Gb/s Transmitter and Receiver Chipset With SFI-5.2 Interface in 40 nm CMOS
Bharath Raghavan,Delong Cui,Ullas Singh,Hassan Maarefi,Deyi Pi,Anand Vasani,Zhi Chao Huang,Burak Catli,Afshin Momtaz,Jun Cao +9 more
TL;DR: The combined transmitter/receiver equalization enables 44.6 Gb/s data transmission using 231-1 PRBS at BER 10-12 over a channel with >21 dB loss at Nyquist frequency.
Journal ArticleDOI
A 3.8 mW/Gbps Quad-Channel 8.5–13 Gbps Serial Link With a 5 Tap DFE and a 4 Tap Transmit FFE in 28 nm CMOS
Namik Kocaman,Tamer Ali,Lakshmi Rao,Ullas Singh,Mohammed Abdul-Latif,Yang Liu,Amr Amin Hafez,Henry Park,Anand Vasani,Zhi Huang,Arvindh Iyer,Bo Zhang,Afshin Momtaz +12 more
TL;DR: This paper presents a quad-lane serial transceiver that supports virtually all data center communication standards around 8.5-13 Gbps, implemented in 28 nm CMOS technology and represents the lowest reported power in its class to date.
Proceedings ArticleDOI
A 3.8 mW/Gbps quad-channel 8.5–13 Gbps serial link with a 5-tap DFE and a 4-tap transmit FFE in 28 nm CMOS
Tamer Ali,Lakshmi Rao,Ullas Singh,Mohammed Abdul-Latif,Yang Liu,Amr Amin Hafez,Henry Park,Anand Vasani,Zhi Huang,Arvindh Iyer,Bo Zhang,Afshin Momtaz,Namik Kocaman +12 more
TL;DR: A quad-lane serial link that supports virtually all data center system-side and line-side communications standards from 8.5-13 Gbps, implemented in 28 nm CMOS with the lowest reported power in its class to date, and with comprehensive programmability for a wide range of standards.