Steep subthreshold swing transistors based on interband tunneling are examined toward extending the performance of electronics systems. In particular, this review introduces and summarizes progress in the development of the tunnel field-effect transistors (TFETs) including its origin, current experimental and theoretical performance relative to the metal-oxide-semiconductor field-effect transistor (MOSFET), basic current-transport theory, design tradeoffs, and fundamental challenges. The promise of the TFET is in its ability to provide higher drive current than the MOSFET as supply voltages approach 0.1 V.

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Low-Voltage Tunnel Transistors for Beyond CMOS Logic

Using calibrated simulations, we report a detailed study of the doping-less tunnel field effect transistor (TFET) on a thin intrinsic silicon film using charge plasma concept. Without the need for any doping, the source and drain regions are formed using the charge plasma concept by choosing appropriate work functions for the source and drain metal electrodes. Our results show that the performance of the doping-less TFET is similar to that of a corresponding doped TFET. The doping-less TFET is expected to be free from problems associated with random dopant fluctuations. Furthermore, fabrication of doping-less TFET does not require a high-temperature doping/annealing processes and therefore cuts down the thermal budget, opening up possibilities for fabricating TFETs on single crystal silicon-on-glass substrates formed by wafer scale epitaxial transfer.

https://web.iitd.ac.in/~mamidala/HTMLobj-1518/dopingless_TFET_TED_Final.pdf

Doping-Less Tunnel Field Effect Transistor: Design and Investigation

In this paper, we propose the application of a dual material gate (DMG) in a tunnel field-effect transistor (TFET) to simultaneously optimize the on-current, the off-current, and the threshold voltage and also improve the average subthreshold slope, the nature of the output characteristics, and immunity against the drain-induced barrier lowering effects. We demonstrate that, if appropriate work functions are chosen for the gate materials on the source side and the drain side, the TFET shows a significantly improved performance. We apply the technique of DMG in a strained double-gate TFET with a high-k gate dielectric to show an overall improvement in the characteristics of the device, along with achieving a good on-current and an excellent average subthreshold slope. The results show that the DMG technique can be applied to TFETs with different channel materials, channel lengths, gate-oxide materials, gate-oxide thicknesses, and power supply levels to achieve significant gains in the overall device characteristics.

Novel Attributes of a Dual Material Gate Nanoscale Tunnel Field-Effect Transistor

In this paper, we present a detailed performance comparison between conventional n-i-n MOSFET transistors and tunneling field-effect transistors (TFETs) based on the p-i-n geometry, using semiconducting carbon nanotubes as the model channel material. Quantum-transport simulations are performed using the nonequilibrium Green's function formalism considering realistic phonon-scattering and band-to-band tunneling mechanisms. Simulations show that TFETs have a smaller quantum capacitance at most gate biases. Despite lower on-current, they can switch faster in a range of on/off-current ratios. Switching energy for TFETs is observed to be fundamentally smaller than that for MOSFETs, leading to lower dynamic power dissipation. Furthermore, the beneficial features of TFETs are retained with different bandgap materials. These reasons suggest that the p-i-n TFET is well suited for low-power applications.

Performance Comparison Between p-i-n Tunneling Transistors and Conventional MOSFETs

Low operating power is an important concern for sub-45-nm CMOS integrated circuits. Scaling of devices to below 45 nm leads to an increase in active power dissipation (CV2.f) and subthreshold power (IOFF.VDD)Hence, new device innovations are being explored to address these problems. In this paper, we simulate and experimentally investigate the source-pocket tunnel field-effect transistor (TFET), which is based on the principle of band-to-band tunneling, p-i-n and source-pocket TFETs are fabricated with different pocket conditions to observe the effect of the source-side pocket on device performance. Different annealing schemes (spike and conventional rapid thermal annealing) are used to study the effect of annealing conditions on TFET performance. The source-pocket TFET shows a higher ION (~10 times) and steeper subthreshold swing as compared to a p-i-n TFET. The ambipolar conduction is also reduced by using a low-doped drain extension. Low-temperature measurements of the source-pocket TFET were performed, and the subthreshold swing of the source-pocket TFET shows very little temperature dependence, which confirms the dominant source injection mechanism to be band-to-band tunneling.

Effect of Pocket Doping and Annealing Schemes on the Source-Pocket Tunnel Field-Effect Transistor

As MOSFET is scaled below 90 nm, many daunting challenges arise. Short-channel effects (SCEs; drain-induced barrier lowering and VTHmiddotrolloff), off-state leakage, parasitic capacitance, and resistance severely limit the performance of these transistors. New device innovations are essential to overcome these difficulties. In this paper, we propose the concept of a novel tunnel source (PNPN) n-MOSFET based on the principle of band-to- band tunneling. It is found that the PNPN n-MOSFET has the potential of steep subthreshold swing and improved Ion in addition to immunities against SCEs. Therefore, such a PNPN n-MOSFET can overcome the ever-degrading on-off characteristics of the deeply scaled conventional MOSFET. The design of the PNPN n-MOSFET was extensively examined using simulations. Devices with source-side tunneling junctions were fabricated on bulk substrates using spike anneal, and the experimental data is presented.

The Tunnel Source (PNPN) n-MOSFET: A Novel High Performance Transistor

Schottky barrier MOSFETs have recently attracted attention as a viable alternative to conventional CMOS transistors for sub-65-nm technology nodes. An asymmetric Schottky tunneling source SOI MOSFET (STS-FET) is proposed in this paper. The Schottky tunneling source SOI MOSFET has the source/drain regions replaced with silicide as opposed to highly doped silicon in conventional devices. The main feature of this device is the concept of a gate-controlled Schottky barrier tunneling at the source. The device was optimized with respect to various parameters such as Schottky barrier height and gate oxide thickness. The optimized device shows excellent short channel immunity, compared to conventional SOI MOSFETs. The asymmetric nature of the device has been shown to improve the leakage current as well as the linear characteristics of the device as compared to conventional Schottky FETs. The STS-FET was fabricated, using conventional processes combined with the present NiSi technology and large angle implantation, and successfully demonstrated. The high immunity to short channel effects improves the scalability, and the output resistance of the device also makes it an attractive candidate for mixed-mode applications.

V. Nagavarapu

Papers

The Tunnel Source (PNPN) n-MOSFET: A Novel High Performance Transistor

Effect of Pocket Doping and Annealing Schemes on the Source-Pocket Tunnel Field-Effect Transistor

Asymmetric Schottky Tunneling Source SOI MOSFET Design for Mixed-Mode Applications