A number of systems and methods, alone, or in combination, achieve various levels of protection against unauthorized modification and distribution of digital content. This encompasses at least unauthorized study, modification, monitoring, reconstruction, and any other means for subversion from the originally intended purpose and license model of the digital content. The invention combines a number of techniques that in whole, or in part, serve to protect such content from unauthorized modification, reconstructive engineering, or monitoring by third parties. This is accomplished by means of methods which protect against subversion by specific tools operating on specific platforms as well as general tools operating on general platforms. Specific time domain attacks are identified, code modification can be identified and reversed, and virtual and emulated systems are identified. In addition, identification of in-circuit emulator tools (both software and hardware), debuggers, and security threats to running programs can be achieved.

Systems and methods for the prevention of unauthorized use and manipulation of digital content

A wafer level fan out package includes a semiconductor die having a first surface, a second surface, and a third surface. A stiffener is disposed on the third surface of the semiconductor die. A conductive via passes through the stiffener. First and second electrically conductive patterns electrically connected to the conductive via are disposed on the first and second surfaces of the semiconductor die and stiffener. Solder balls are electrically connected to the first or second electrically conductive patterns.

Fan-out semiconductor package

Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of 1-Gigabyte and 2-Gigabyte capacity memory modules. A first row of integrated circuits is oriented in an opposite orientation to a second row of integrated circuits. The integrated circuits in a first half of the first row and in the corresponding half of the second row are connected via a signal trace to a first register. The integrated circuits in a second half of the first row and in the corresponding half of the second row are connected to a second register. Each register processes a non-contiguous subset of the bits in each data word.

Arrangement of integrated circuits in a memory module

A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.

Through-wafer interconnects for photoimager and memory wafers

A light-emitting device package including a lead frame formed of a metal and on which a light-emitting device chip is mounted; and a mold frame coupled to the lead frame by injection molding. The lead frame includes: a mounting portion on which the light-emitting device chip is mounted; and first and second connection portions that are disposed on two sides of the mounting portion in a first direction and connected to the light-emitting device chip by wire bonding, wherein the first connection portion is stepped with respect to the mounting portion, and a stepped amount is less than a material thickness of the lead frame.

Semiconductor package and method of manufacturing the same

The present invention includes methods for making liquid crystalline polymer (LCP) interconnect structures using a high temperature and low temperature single sided LCP, where both the high and low temperature LCP are provided with a z-axis connection. The single sided conductive layer is a bus layer to form z-axis conductive stud within the high and low temperature LCP. High and low temperature LCP layers are etched or built up to form circuit patterns and subsequently bonded together to form final multilayer circuit pattern where the low temperature LCP melts to form both dielectric to dielectric bond to high temperature LCP circuit layer, and dielectric to conductive bond.

Methods for fabricating three-dimensional all organic interconnect structures

The present invention provides all organic fully-packaged miniature bandpass filters, baluns, diplexers, multiplexers, couplers and a combination of the above manufactured using liquid crystalline polymer (LCP) and other multilayer polymer based substrates These devices are manufactured using one or more LCP layers having integrated passive components formed thereon to provide the density and performance necessary for multi-band wireless devices In the designs involving multiple LCP layers, the LCP layers are separated by prepeg layers In accordance with an aspect of the present invention, coplanar waveguide, hybrid stripline/coplanar waveguide and/or microstrip topologies are utilized to form the integrated passive components, and the devices can be mass produced on large area panels at least 18 inches by 12 inches with line widths smaller than 10 um

Liquid crystalline polymer and multilayer polymer-based passive signal processing components for RF/wireless multi-band applications

The present invention includes an organic device that can be integrated in a multilayer board made of organic material. The passive devices can be integrally fabricated on a circuit board in either surface mount device (SMD) or ball grid array (BGA) form. Alternatively, the passive device can be constructed in a stand alone SMD or BGA/chip scale package (CSP) form to make it mountable on a multilayer board, ceramic carrier or silicon platform in the form of an integrated passive device. The passive device includes side shielding on two sides in the SMD form and four sides in the BGA/CSP form. The side shielding can be external or in-built.

Integrated passive devices fabricated utilizing multi-layer, organic laminates

Failure analysis of through-silicon vias in free-standing wafer under thermal-shock test

The present invention provides for low cost discrete inductor devices in an all organic platform. The inductor devices can utilize virtually any organic material that provides the desired properties, such as liquid crystalline polymer (LCP) or polyphenyl ether (PPE), in a multilayer structure, wherein the organic materials have low moisture uptake and good temperature stability. Each layer may be metalized and selectively interconnected by vias formed in respective layers so as to form winding or coiled inductors. The inductor devices may advantageously include external shielding formed by metalizing the side walls and top surface of the inductor devices on in-built shielding achieved by the utilization of the hybrid co-planar waveguide topologies. The inductor devices can be configured for either ball grid array (BGA)/chip scale package (CSP) or surface mount device (SMD) mounting to circuit boards.

Venkatesh Sundaram

Papers

Methods for fabricating three-dimensional all organic interconnect structures

Liquid crystalline polymer and multilayer polymer-based passive signal processing components for RF/wireless multi-band applications

Integrated passive devices fabricated utilizing multi-layer, organic laminates

Failure analysis of through-silicon vias in free-standing wafer under thermal-shock test

Stand-alone organic-based passive devices