A system for analyzing IC layouts and designs by calculating variations of a number of objects to be created on a semiconductor wafer as a result of different process conditions. The variations are analyzed to determine individual feature failures or to rank layout designs by their susceptibility to process variations. In one embodiment, the variations are represented by PV-bands having an inner edge that defines the smallest area in which an object will always print and an outer edge that defines the largest area in which an object will print under some process conditions.

Integrated circuit layout design methodology with process variation bands

A semiconductor device includes a substrate and a number of diffusion regions defined within the substrate. The diffusion regions are separated from each other by a non-active region of the substrate. The semiconductor device includes a number of linear gate electrode tracks defined to extend over the substrate in a single common direction. Each linear gate electrode track is defined by one or more linear gate electrode segments. Each linear gate electrode track that extends over both a diffusion region and a non-active region of the substrate is defined to minimize a separation distance between ends of adjacent linear gate electrode segments within the linear gate electrode track, while ensuring adequate electrical isolation between the adjacent linear gate electrode segments.

Dynamic array architecture

A method of designing an integrated circuit is provided in which the design layout is optimized using a process model until the design constraints are satisfied by the image contours simulated by the process model. The process model used in the design phase need not be as accurate as the lithographic model used in preparing the lithographic mask layout during data prep. The resulting image contours are then included with the modified, optimized design layout to the data prep process, in which the mask layout is optimized using the lithographic process model, for example, including RET and OPC. The mask layout optimization matches the images simulated by the lithographic process model with the image contours generated during the design phase, which ensures that the design and manufacturability constraints specified by the designer are satisfied by the optimized mask layout.

Closed-loop design for manufacturability process

A method and apparatus for inspecting a photolithography mask for defects is provided. The inspection method comprises providing a defect area image to an image simulator wherein the defect area image is an image of a portion of a photolithography mask, and providing a set of lithography parameters as a second input to the image simulator. The defect area image may be provided by an inspection tool which scans the photolithography mask for defects using a high resolution microscope and captures images of areas of the mask around identified potential defects. The image simulator generates a first simulated image in response to the defect area image and the set of lithography parameters. The first simulated image is a simulation of an image which would be printed on a wafer if the wafer were to be exposed to an illumination source directed through the portion of the mask. The method may also include providing a second simulated image which is a simulation of the wafer print of the portion of the design mask which corresponds to the portion represented by the defect area image. The method also provides for the comparison of the first and second simulated images in order to determine the printability of any identified potential defects on the photolithography mask. A method of determining the process window effect of any identified potential defects is also provided for.

Visual inspection and verification system

A method is disclosed for defining a dynamic array section to be manufactured on a semiconductor chip. The method includes defining a peripheral boundary of the dynamic array section. The method also includes defining a manufacturing assurance halo outside the boundary of the dynamic array section. The method further includes controlling chip layout features within the manufacturing assurance halo to ensure that manufacturing of conductive features inside the boundary of the dynamic array section is not adversely affected by chip layout features within the manufacturing assurance halo.

Methods for Defining Dynamic Array Section with Manufacturing Assurance Halo and Apparatus Implementing the Same

Subwavelength lithography at low contrast, or low-k1 factor, leads to new requirements for design, design analysis, and design verification techniques. These techniques must account for inherent physical circuit feature distortions resulting from layout pattern-dependent design-to-silicon patterning processes in this era. These
distortions are unavoidable, even in the presence of sophisticated Resolution Enhancement Technologies (RET), and are a 'fact-of-life’ for the designer implementing nanometer-scale designs for the foreseeable low-k1 future. The consequence is that fabricated silicon feature shapes and dimensions are in general printed with far less
fidelity in comparison to the designer’s desired layout than in past generations and that the designer must consider design within significantly different margins of geometry tolerance. Traditional (Mead-Conway originated) WYSIWYG (what you see is what you get) design methodologies, assume that the designer’s physical circuit element shapes are accurate in comparison to the corresponding shapes on the real fabricated IC, and uses design rules to verify satisfactory fabrication compliance, as the input for both
interconnect parasitic loading calculations and to transistor models used for performance simulation. However, these assumptions are increasingly poor ones as k1 decreases to unprecidented levels -- with concomitant increase in patterned feature distortion and fabrication yield failure modes. This paper explores a new paradigm for nanometer-scale design, one in which more advanced models of critical low-k1 lithographic printing effects are incorporated into the design flow to improve upon yield and performance verification accuracy. We start with an analysis of a complex 32-bit adder block circuit design to determine systematic changes in gate length, width and shape variations for each MOSFET in the circuit due to optical
proximity effects. The physical gate dimensions for all, as predicted by the simulations, are then incorporated into the circuit simulation models and netlist (schematic) and are used to calculate the changes in critical parametric yield factors such as timing and power consumption in the circuit behavior. These functional consequences create a manufacturability tolerance requirement that relates to function and parametric yield, not just physical manufacturability. We then explore the improvements in functional attributes and manufacturability that arise from systematic correction of these distortions by RET including; simulation-driven model-based OPC,
alternating-aperture PSM (altPSM), and altPSM+OPC. This analysis is just one dimension of a systmatic methodology that incorporates lithographic effects into a design for manufacturing (DFM) scheme. The benefits promise dramatically improved silicon-signoff verification, predictive performance and yield analysis, and more
cost-effective application of RET.

Physical and timing verification of subwavelength-scale designs: I. Lithography impact on MOSFETs

A method for performing self-consistent minimization of IC design and process interactions is disclosed. This method is based on calculating the amount of design-process interaction based on the information derived from circuit sensitivity analysis and process characterization. Optical proximity correction is subsequently performed in such a way that a) ensures that desired circuit performance is achieved in a given manufacturing environment if at all possible and b) also limits the increase in mask complexity to a realistic minimum.

Integrated scheme for yield improvement by self-consistent minimization of IC design and process interactions

Accurate manufacturing of devices at sub-wavelength nodes is becoming increasingly difficult. Lithography and lithographic process effects are quickly becoming a major concern for physical designers working at sub-wavelength process nodes. Beyond the rapidly expanding design rule deck, physical designers must have deeper access to and understanding of the process in order to grasp the full impact of layout changes on electrical performance. Process aberrations, such as misalignment, are manifested as CD variation resulting in parametric shifts and systematic yield problems. These yield issues must be addressed by designers, but designers do not have adequate tools nor information to fully comprehend these issues. To correct this situation, a new approach is needed to bring information from the manufacturing process upstream into the design creation process. This work extends and generalizes concepts presented in [1-3] and presents an integrated implementation of the methodology in a complete, self-consistent flow. This methodology integrates calibrated process simulation, electrical circuit performance analysis and optionally, automatic Optical Proximity Correction (OPC) into a comprehensive Design-for-Manufacturing (DFM) flow. Process window simulations uncover design-process interactions across multiple process variables (misalignment, bias, etc.). To characterize the process, a design of experiments qualifies the impact of design variation on electrical performance. Data from these experiments is used to refine and calibrate process simulation models, ensuring accurate simulation. As a result, this procedure identifies critical performance and systematic yield issues prior to tapeout, eliminating costly design respins and preserving design intent.

A novel design-process optimization technique based on self-consistent electrical performance evaluation

A method has been developed that allows accurate simulation of pattern profiles in photoresist in excess of 10 micrometer thick. The method uses the DEPICTR photolithography simulator to model i-line exposure, bake and development of Shipley SJRR5740 thick film photoresists with an Ultratech 2244i Wafer StepperR. Kim model inputs were estimated from a family of development rate curves obtained by processing wafers with a range of expose energies for logarithmically increasing develop times and measuring thickness change as the develop process occurred. These results were compared with dissolution results obtained using a laser-based dissolution rate monitor. Uncertainties in the measured photoresist absorbence, photosensitivity and refractive index coefficients were estimated and their influence on the simulated results were considered. An optimization procedure and algorithm that allows quantitative comparison of experimental and simulated photoresist profiles is presented. Simulated photoresist profiles were compared with patterns obtained from processed wafers. As a further test of the models, pattern profiles were simulated for 2 micrometer spaces in 10 micrometer thick photoresist through focus. Experimental and simulated pattern profiles from a range of exposure doses were also compared.

Victor V. Boksha

Papers

Physical and timing verification of subwavelength-scale designs: I. Lithography impact on MOSFETs

Integrated scheme for yield improvement by self-consistent minimization of IC design and process interactions

A novel design-process optimization technique based on self-consistent electrical performance evaluation

Advanced simulation techniques for thick photoresist lithography

Dry patterning through masks of organic materials