Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

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High-κ gate dielectrics: Current status and materials properties considerations

An electrically erasable programmable read only memory (EEPROM) having a non conducting charge trapping dielectric, such as silicon nitride, sandwiched between two silicon dioxide layers acting as electrical insulators is disclosed. The invention includes a method of programming, reading and erasing the EEPROM device. The non conducting dielectric layer functions as an electrical charge trapping medium. A conducting gate layer is placed over the upper silicon dioxide layer. The memory device is programmed in the conventional manner, using hot electron programming, by applying programming voltages to the gate and the drain while the source is grounded. Hot electrons are accelerated sufficiently to be injected into the region of the trapping dielectric layer near the drain. The device, however, is read in the opposite direction from which it was written, meaning voltages are applied to the gate and the source while the drain is grounded. Application of relatively low gate voltages combined with reading in the reverse direction greatly reduces the potential across the trapped charge region. This permits much shorter programming times by amplifying the effect of the charge trapped in the localized trapping region. In addition, the memory cell can be erased by applying suitable erase voltages to the gate and the drain so as to cause electrons to be removed from the charge trapping region of the nitride layer. Similar to programming, a narrower charge trapping region enables much faster erase cycles.

Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping

A nitride programmable read only memory (NROM) cell with a pocket implant self-aligned to at least one bit line junction. Alternatively, the bit line junction(s) can have a thin area of effective programming and erasing located nearby. Further alternatively, the channel can have a threshold voltage level implant which has a low voltage level in a central area of the channel and which has a peak of high voltage level near at least one of the bit line junctions. With one pocket implant, the NROM cell stores one bit. With two pocket implants, the NROM cell stores two bits.

NROM cell with improved programming, erasing and cycling

In an active matrix display device, a circuit including at least five thin film transistors (TFTs) which are provided with an approximately M-shaped semiconductor region for a single pixel electrode and gate lines and a capacitances line which cross the M-shaped semiconductor region, is used as a switching element. Each of the TFT have offset regions and lightly doped drain (LDD) regions. Then, by supplying a selection signal to the gate lines, the TFTs are operated, thereby writing data to the pixel, while a suitable voltage is supplied to the capacitance line, a channel is formed thereunder and it becomes a capacitor. Thus the amount of discharge from the pixel electrode is reduced by the capacitor.

Active matrix display device

The invention includes semiconductor constructions containing vertically-extending pillars, and methods for forming such constructions. The vertically-extending pillars can be incorporated into transistor devices, and can contain vertically-extending channel regions of the transistor devices. The transistor devices can be incorporated into integrated circuitry, and in some aspects are incorporated into memory constructions, such as, for example, dynamic random access memory (DRAM) constructions.

Methods of forming semiconductor constructions

Vertical nMOS transistors with channel lengths down to 70 nm and thin gate oxides have been fabricated using LPCVD epitaxy for the definition of the channel region instead of fine line lithography. The devices show drain current and transconductance values comparable to very advanced planar transistors. For the shortest channel length a very strong increase of saturation current is observed and is attributed to V/sub t/ shift and floating substrate effects. Moreover, transconductance may indicate ballistic overshoot. Besides high saturation currents due to very short channel lengths higher integration density seems to be very attractive for special applications.

Vertical MOS transistors with 70 nm channel length

A read-only-memory cell arrangement comprises memory cells, each having a vertical MOS transistor, in a substrate (21) made of semiconductor material, the various logic values (zero, one) being implemented by gate dielectrics (27, 28) of different thickness. The memory cell arrangement can preferably be produced in a silicon substrate, with a small number of process steps and a high packing density. The memory cell arrangement and a drive circuit for read-out can in this case be produced in an integrated manner.

Read-only-memory cell arrangement using vertical MOS transistors and gate dielectrics of different thicknesses and method for its production

Eine Festwert-Speicherzellenanordnung umfast in einem Substrat (21) aus Halbleitermaterial Speicherzellen mit jeweils einem vertikalen MOS-Transistor, wobei die verschiedenen logischen Werte (Null, Eins) durch unterschiedlich dicke Gatedielektrika (27, 28) realisiert werden. Die Speicherzellenanordnung last sich insbesondere in einem Siliziumsubstrat mit wenigen Prozesschritten und hoher Packungsdichte herstellen. Die Speicherzellenanordnung und eine Ansteuerschaltung zum Auslesen konnen dabei integriert hergestellt werden.

Festwert-speicherzellenanordnung und verfahren zu deren herstellung

The method produces an opening in a layered semiconductor structure having a site intended for an opening. A place-saver is produced on the structure from a first material to be selectively etched to the structure under the first material and to a material adjacent the site. A layer of a second material to which the first material is selectively etchable, is produced over the entire surface of the structure having the place-saver. The opening is formed by at least partially removing the layer of the second material above the place-saver, and removing the place-saver by selective etching.

Method for producing an opening in a layered semiconductor structure or a contact hole in an integrated circuit or DRAM

A method for production of a read-only-memory cell arrangement having vertical MOS transistors is provided. In order to produce a read-only-memory cell arrangement which has first memory cells having a vertical MOS transistor and second memory cells which do not have a vertical MOS transistor, holes provided with a gate dielectric and a gate electrode are etched in a silicon substrate with a layer sequencing corresponding to a source, a channel and a drain for the first memory cells. Insulation trenches whose separation is preferably equal to their width are produced for insulation of adjacent memory cells.

W. Rosner

Papers

Vertical MOS transistors with 70 nm channel length

Read-only-memory cell arrangement using vertical MOS transistors and gate dielectrics of different thicknesses and method for its production

Festwert-speicherzellenanordnung und verfahren zu deren herstellung

Method for producing an opening in a layered semiconductor structure or a contact hole in an integrated circuit or DRAM

Method for production of a read-only-memory cell arrangement having vertical MOS transistors