Many materials systems are currently under consideration as potential replacements for SiO2 as the gate dielectric material for sub-0.1 μm complementary metal–oxide–semiconductor (CMOS) technology. A systematic consideration of the required properties of gate dielectrics indicates that the key guidelines for selecting an alternative gate dielectric are (a) permittivity, band gap, and band alignment to silicon, (b) thermodynamic stability, (c) film morphology, (d) interface quality, (e) compatibility with the current or expected materials to be used in processing for CMOS devices, (f) process compatibility, and (g) reliability. Many dielectrics appear favorable in some of these areas, but very few materials are promising with respect to all of these guidelines. A review of current work and literature in the area of alternate gate dielectrics is given. Based on reported results and fundamental considerations, the pseudobinary materials systems offer large flexibility and show the most promise toward success...

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High-κ gate dielectrics: Current status and materials properties considerations

The invention includes semiconductor constructions containing vertically-extending pillars, and methods for forming such constructions. The vertically-extending pillars can be incorporated into transistor devices, and can contain vertically-extending channel regions of the transistor devices. The transistor devices can be incorporated into integrated circuitry, and in some aspects are incorporated into memory constructions, such as, for example, dynamic random access memory (DRAM) constructions.

Methods of forming semiconductor constructions

Methods of forming a nano-scale electronic and optoelectronic devices include forming a substrate having a semiconductor layer therein and a substrate insulating layer on the semiconductor layer. An etching template having a first array of non-photolithographically defined nano-channels extending therethrough, is formed on the substrate insulating layer. This etching template may comprise an anodized metal oxide, such as an anodized aluminum oxide (AAO) thin film. The substrate insulating layer is then selectively etched to define a second array of nano-channels therein. This selective etching step preferably uses the etching template as an etching mask to transfer the first array of nano-channels to the underlying substrate insulating layer, which may be thinner than the etching template. An array of semiconductor nano-pillars is then formed in the second array of nano-channels. The semiconductor nano-pillars in the array may have an average diameter in a range between about 8 nm and about 50 nm. The semiconductor nano-pillars are also preferably homoepitaxial or heteroepitaxial with the semiconductor layer.

Optoelectronic devices having arrays of quantum-dot compound semiconductor superlattices therein

A memory device includes a diode driver and a data storage element, such as an element comprising phase change memory material, and in which the diode driver comprises a silicide element on a silicon substrate with a single crystal silicon node on the silicide element. The silicide element separates the single crystal silicon node from the underlying silicon substrate, preventing the flow of carriers from the single crystal silicon node into the substrate, and is capable of acting as a conductive element for interconnecting devices on the device. The single crystal silicon node acts as one terminal of a diode, and a second semiconductor node is formed on top of it, acting as the other terminal of the diode.

Integrated circuit memory with single crystal silicon on silicide driver and manufacturing method

This thesis discusses device physics, modeling and design issues of nanoscale transistors at the quantum level. The principle topics addressed in this report are 1) an implementation of appropriate physics and methodology in device modeling, 2) development of a new TCAD (technology computer aided design) tool for quantum level device simulation, 3) examination and assessment of new features of carrier transport in nano-scale transistors, and 4) exploration of device design issues near the ultimate scaling limit with the help of the developed tools. We concentrate on the technical issues by investigating a double-gate structure, which has been widely accepted as the ideal device structure for ultimate CMOS scaling. We focus on quantum effects and non-equilibrium, near-ballistic transport in extremely scaled transistors (in contrast to quasi-equilibrium, scattering-dominant transport in long channel devices), where a non-equilibrium Green’s function formalism (NEGF) has been used to deal with the quantum transport problem.

Nanoscale MOSFETS: Physics, Simulation and Design

Vertical nMOS transistors with channel lengths down to 70 nm and thin gate oxides have been fabricated using LPCVD epitaxy for the definition of the channel region instead of fine line lithography. The devices show drain current and transconductance values comparable to very advanced planar transistors. For the shortest channel length a very strong increase of saturation current is observed and is attributed to V/sub t/ shift and floating substrate effects. Moreover, transconductance may indicate ballistic overshoot. Besides high saturation currents due to very short channel lengths higher integration density seems to be very attractive for special applications.

Vertical MOS transistors with 70 nm channel length

Vertical nMOS transistors with channel lengths down to 70nm and thin gate oxides have been fabricated using LPCVD epitaxy for the definition of the channel region instead of fine line lithography. The devices show drain current and transconductance values comparable to very advanced planar transistors. For the shortest channel length a stronger increase of current is observed and is attributed to ballistic and floating substrate effects. Besides high saturation currents due to very short channel lengths a higher integration density seems to be feasible using this vertical transistor technology.

https://ieeexplore.ieee.org/iel5/5435865/5435866/05436000.pdf

Vertical MOS Transistors with 70nm Channel Length

A dynamic gain memory cell has been fabricated which, despite its planar design, can compete with the area requirements of one transistor DRAM cells (1T-cells) built in trench or 3D stacked technology. The described gain cell can be geometrically shrunk because the drain current of scaled down MOS transistors increases resulting in higher signal charge. Another attractive feature of the proposed gain memory cell is that it can be fabricated using a CMOS logic process to bridge the gap between DRAM and CMOS logic technology. Because of its inherent amplification, the gain cell delivers even at supply voltages below 2 V sufficient signal charge making it suitable for low voltage applications.

Planar gain cell for low voltage operation and gigabit memories

Simulation of single electron circuits

Vertical MOS transistors are a promising approach for channel lengths in the range of 100 to 25nm without the need for extreme fine line lithography. These devices provide high satura­ tion currents due to the short channel length and small lateral size due to the 3Dgeometry. The channel is defined by epitaxy which can be grown with very good layer thickness control and various doping concentrations. The doping profiles and electrical characteristics of the transistors are investigated and possible applications for high speed logic and small memory cells will be

L. Risch

Papers

Vertical MOS transistors with 70 nm channel length

Vertical MOS Transistors with 70nm Channel Length

Planar gain cell for low voltage operation and gigabit memories

Simulation of single electron circuits

Recent Progress with Vertical Transistors