Semiconductor nanowires have attracted extensive interest as one of the best-defined classes of nanoscale building blocks for the bottom-up assembly of functional electronic and optoelectronic devices over the past two decades. The article provides a comprehensive review of the continuing efforts in exploring semiconductor nanowires for the assembly of functional nanoscale electronics and macroelectronics. Specifically, we start with a brief overview of the synthetic control of various semiconductor nanowires and nanowire heterostructures with precisely controlled physical dimension, chemical composition, heterostructure interface, and electronic properties to define the material foundation for nanowire electronics. We then summarize a series of assembly strategies developed for creating well-ordered nanowire arrays with controlled spatial position, orientation, and density, which are essential for constructing increasingly complex electronic devices and circuits from synthetic semiconductor nanowires. Next, we review the fundamental electronic properties and various single nanowire transistor concepts. Combining the designable electronic properties and controllable assembly approaches, we then discuss a series of nanoscale devices and integrated circuits assembled from nanowire building blocks, as well as a unique design of solution-processable nanowire thin-film transistors for high-performance large-area flexible electronics. Last, we conclude with a brief perspective on the standing challenges and future opportunities.

Nanowire Electronics: From Nanoscale to Macroscale

Low-dimensional semiconductor materials structures, where nanowires are needle-like one-dimensional examples, have developed into one of the most intensely studied fields of science and technology. The subarea described in this review is compound semiconductor nanowires, with the materials covered limited to III-V materials (like GaAs, InAs, GaP, InP,...) and III-nitride materials (GaN, InGaN, AlGaN,...). We review the way in which several innovative synthesis methods constitute the basis for the realization of highly controlled nanowires, and we combine this perspective with one of how the different families of nanowires can contribute to applications. One reason for the very intense research in this field is motivated by what they can offer to main-stream semiconductors, by which ultrahigh performing electronic (e.g., transistors) and photonic (e.g., photovoltaics, photodetectors or LEDs) technologies can be merged with silicon and CMOS. Other important aspects, also covered in the review, deals with synthesis methods that can lead to dramatic reduction of cost of fabrication and opportunities for up-scaling to mass production methods.

Synthesis and Applications of III-V Nanowires

Perovskite nanostructures have attracted much attention in recent years due to their suitability for a variety of applications such as photovoltaics, light-emitting diodes (LEDs), nanometer-size lasing, and more. These uses rely on the conductive properties of these nanostructures. However, electrical characterization of individual, thin perovskite nanowires has not yet been reported. Here, conductive atomic force microscopy characterization of individual cesium lead halide nanowires is presented. Clear differences are observed in the conductivity of nanowires containing only bromide and nanowires containing a mixture of bromide and iodide. The differences are attributed to a higher density of crystalline defects, deeper trap states, and higher inherent conductivity for nanowires with mixed bromide-iodide content.

Electrical Characterization of Individual Cesium Lead Halide Perovskite Nanowires Using Conductive AFM.

This thesis describes charge transport in III-V narrow bandgap semiconductor nanowires. We are particularly interested in quantum transport in InSb, InAs and InP-InAs core-shell nanowires. According to the type of transport mechanism dominating in the devices, this thesis can be divided into four parts.In the first part of this thesis, we investigated the temperature dependent transport properties of InSb nanowires using field effect transistors made of InSb nanowires grown by chemical vapor deposition. Ambipolar transport is observed in measurements in a wide range of temperatures up to 300 K. A bandgap of 220 meV is extracted from the temperature dependent measurements. Hole and electron field effect mobility are determined and their temperature dependence studied. The off state current shows a strong dependence on the temperature and the channel lengths of the transistors. In the second part of this thesis, spin relaxation and quantum interference in InSb nanowires are explored. Low-field magneto-conductance measurements are performed and a crossover from weak antilocalization to weak localization is observed. The experimental results are well explained with quasi one dimensional weak localization theory. Spin relaxation length and phase coherence length are defined. A strong spin-orbit strength of αR = 0.4 eVÅ-0.87 eVÅ is extracted. In the third part of this thesis, electron transport in a single quantum dot is studied in the weak and strong dot coupling regimes. The single quantum dots are formed in InSb nanowires by side gates. Various transport features such as sequential tunneling, excited states, and cotunnelings are investigated. Low temperature transport properties of InP-InAs core-shell nanowires are also explored and the coulomb blockade effect is revealed from a quantum structure extending over the entire core-shell nanowire. In the last part of this thesis, we report on electron transport through double quantum dots in InSb and InAs nanowires defined by side gates. From the measurements in the weak inter dot coupling regime, Pauli spin blockade is observed. The evolutions of states in the Pauli spin-blockade region with magnetic field is also studied. (Less)

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Charge transport in III-V narrow bandgap semiconductor nanowires

We report gold-free growth of vertically aligned InAs/GaSb heterostructure nanowires (NWs) on Si(111) substrate by metal organic chemical vapor deposition technique. The effect of growth temperature on morphology and growth rate for InAs and InAs/GaSb heterostructure NWs were investigated. A combination of high material flow rates and optimum temperature (600 °C) has given better crystal quality of InAs nanowires. The morphology and shell thickness of NWs as observed by scanning electron microscope and transmission electron microscope (TEM) measurements can be tuned by the growth temperature. Electron microscopy also shows the formation of GaSb both in radial and axial directions outside the InAs NW core at certain growth temperatures. Crystal structure of InAs and InAs/GaSb heterostructure NWs was analyzed by high-resolution TEM and fast Fourier transform analysis. Using good crystalline InAs core grown at optimized growth temperature (600 °C), GaSb shell has been grown without any misfit dislocations at the core-shell interface. Basic electrical properties have been measured by forming ohmic contacts. I–V characteristics exhibit linear response indicating good ohmic behavior. These results show good control over InAs NWs growth, the GaSb shell thickness, and its crystal quality, which are essential for future nanoelectronic devices such as tunneling FET.

Growth and Crystal Structure Investigation of InAs/GaSb Heterostructure Nanowires on Si Substrate

The excess OFF-state current caused by band to band tunneling (BTBT) is a serious issue particularly in short-channel nanowire (NW) field-effect transistors (FETs), especially for narrow bandgap semiconductors such as InAs. Here, to clarify the components of the OFF-current and suppress the OFF-current, we for the first time fabricate and study InAs NW FETs with nanoscale partial-gate (PG). We fabricate a series of PGFETs and a normal full-gate (FG) FET on the same NW. Based on our results, the BTBT current component can reach tens of nanoamps in a typical 250 nm-channel InAs NW FGFET, and dominate the OFF-current. In contrast, there is almost no BTBT component in the PGFET, which provides a reference for other short-channel InAs NW FETs. Furthermore, the physical mechanism of the OFF-state carrier transport is discussed, and both electrons and holes currents are proven to be very important, based on our experimental results. Also, through statistic study, we find the BTBT effect can be more serious in the devices with better gate-control. Therefore, suppressing the BTBT effect is important to the future scaling-down.

https://iopscience.iop.org/article/10.1088/1361-6528/aad67c/pdf

Suppressing the excess OFF-state current of short-channel InAs nanowire field-effect transistors by nanoscale partial-gate

Effect of nanohole size on selective area growth of InAs nanowire arrays on Si substrates

We reported here a selectively additive process to fabricate nanoscale openings of an Si (111) surface from an SiO2 barrier layer. Such nanoscale openings are made for the growth of vertical III–V nanowires. The Si (111) surface protected by a patterned SiNx layer was thermally oxidized, which resulted in a selectively added SiO2 barrier layer. After removing the SiNx, nanoscale openings of the Si (111) surface were exposed for the nanowire growth. Arrays with patterned nanoholes of varied diameters from 60 nm to 334 nm have been used for position-controlled catalyst-free growth of vertical InAs nanowire arrays by metal-organic chemical vapor deposition. Correlations between the nanohole diameter and the diameter, length and growth yield of as-fabricated nanowire arrays have been investigated, showing a repeatable stability. This technique offers an alternative approach for the fabrication of novel III–V nanowire devices using vertical array configuration. A lateral thermal oxidation effect led to a smaller size of the Si opening than that of the SiNx protection nanoislands; therefore, the technique also offers a controllable way to produce nanoholes with an ultra-small diameter.

Nanoscale opening fabrication on Si (111) surface from SiO2 barrier for vertical growth of III-V nanowire arrays

We find the nanoscale steps on Si (1 1 1) surface can influence the self-catalyzed position-controlled InAs nanowire growth by metal-organic chemical vapor deposition (MOCVD). The nanoscale steps, made of the photoresist residues induced by incomplete-development after electron beam lithography, show a strong effect on the size and density of InAs nanowire nucleation. The phenomena are explained by a proposed model that the nanoscale steps on Si (1 1 1) surface can block the diffusion of Indium atoms thus influencing the formation of Indium droplets. Our result is helpful for understanding the growing mechanism and growing InAs nanowires with precise position-control.

https://iopscience.iop.org/article/10.1088/1361-6439/aa9c1e/pdf

The effect of nanoscale steps on the self-catalyzed position-controlled InAs nanowire growth

With the scaling down of field-effect transistors (FETs) to improve their performance, 3D vertical surrounding gate structure has drawn great attention. On the other hand, concerning the channel materials, InAs nanowires (NWs) have been demonstrated to have great potential in FET due to their high mobility and other excellent electrical properties. Here, we report the first all-metal electrodes vertical gate-allaround (VGAA) FET fabricated using self-catalyzed selective grown InAs NWs array grown by metal organic chemical vapor deposition. A typical transistor we fabricated has an on-state current larger than 37 μA/μm when the drain voltage and gate voltage are +0.6 V and +3.0 V, respectively, and an on-off ratio over 3 orders of magnitudes. We have measured 34 transistors in total, and most of them have the on-off ratio between 102 and 104. Annealing is observed to improve the contact property, increase the on-state current, but decrease the on-off ratio. The ways to improve the performance of InAs NW VGAA FET are discussed.

Wenyuan Yang

Papers

Suppressing the excess OFF-state current of short-channel InAs nanowire field-effect transistors by nanoscale partial-gate

Effect of nanohole size on selective area growth of InAs nanowire arrays on Si substrates

Nanoscale opening fabrication on Si (111) surface from SiO2 barrier for vertical growth of III-V nanowire arrays

The effect of nanoscale steps on the self-catalyzed position-controlled InAs nanowire growth

All-metal electrodes vertical gate-all-around device with self-catalyzed selective grown InAs NWs array