Rapid progress in the synthesis and processing of materials with structure on nanometer length scales has created a demand for greater scientific understanding of thermal transport in nanoscale devices, individual nanostructures, and nanostructured materials. This review emphasizes developments in experiment, theory, and computation that have occurred in the past ten years and summarizes the present status of the field. Interfaces between materials become increasingly important on small length scales. The thermal conductance of many solid–solid interfaces have been studied experimentally but the range of observed interface properties is much smaller than predicted by simple theory. Classical molecular dynamics simulations are emerging as a powerful tool for calculations of thermal conductance and phonon scattering, and may provide for a lively interplay of experiment and theory in the near term. Fundamental issues remain concerning the correct definitions of temperature in nonequilibrium nanoscale systems. Modern Si microelectronics are now firmly in the nanoscale regime—experiments have demonstrated that the close proximity of interfaces and the extremely small volume of heat dissipation strongly modifies thermal transport, thereby aggravating problems of thermal management. Microelectronic devices are too large to yield to atomic-level simulation in the foreseeable future and, therefore, calculations of thermal transport must rely on solutions of the Boltzmann transport equation; microscopic phonon scattering rates needed for predictive models are, even for Si, poorly known. Low-dimensional nanostructures, such as carbon nanotubes, are predicted to have novel transport properties; the first quantitative experiments of the thermal conductivity of nanotubes have recently been achieved using microfabricated measurement systems. Nanoscale porosity decreases the permittivity of amorphous dielectrics but porosity also strongly decreases the thermal conductivity. The promise of improved thermoelectric materials and problems of thermal management of optoelectronic devices have stimulated extensive studies of semiconductor superlattices; agreement between experiment and theory is generally poor. Advances in measurement methods, e.g., the 3ω method, time-domain thermoreflectance, sources of coherent phonons, microfabricated test structures, and the scanning thermal microscope, are enabling new capabilities for nanoscale thermal metrology.

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Nanoscale thermal transport

The present invention provides stretchable, and optionally printable, semiconductors and electronic circuits capable of providing good performance when stretched, compressed, flexed or otherwise deformed. Stretchable semiconductors and electronic circuits of the present invention preferred for some applications are flexible, in addition to being stretchable, and thus are capable of significant elongation, flexing, bending or other deformation along one or more axes. Further, stretchable semiconductors and electronic circuits of the present invention may be adapted to a wide range of device configurations to provide fully flexible electronic and optoelectronic devices.

http://science.sciencemag.org/content/sci/311/5758/208.full.pdf

Stretchable form of single crystal silicon for high performance electronics on rubber substrates

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

Semiconductor nanowires represent an important class of nanostructure building block for photovoltaics as well as direct solar-to-fuel application because of their high surface area, tunable bandgap and efficient charge transport and collection. In this talk, I will highlight several recent examples in this lab using semiconductor nanowires and their heterostructures for the purpose of solar energy harvesting. In addition, we have also discovered that the thermoconductivity of the silicon nanowires can be significantly reduced due to phonon scattering, pointing to a very promising approach to design better thermoelectrical materials. It is important to note that the engines that generate most of the world's power typically operate at only 30–40 per cent efficiency, releasing roughly 15 terawatts of heat to the environment. If this “wasted heat” could be recycled, the impact globally would be enormous. Our silicon nanowire thermoelectric technology could have a significant impact in alternative energy generation.

Semiconductor nanowires for energy conversion.

The present invention provides methods, systems and system components for transferring, assembling and integrating features and arrays of features having selected nanosized and/or microsized physical dimensions, shapes and spatial orientations. Methods of the present invention utilize principles of ‘soft adhesion’ to guide the transfer, assembly and/or integration of features, such as printable semiconductor elements or other components of electronic devices. Methods of the present invention are useful for transferring features from a donor substrate to the transfer surface of an elastomeric transfer device and, optionally, from the transfer surface of an elastomeric transfer device to the receiving surface of a receiving substrate. The present methods and systems provide highly efficient, registered transfer of features and arrays of features, such as printable semiconductor element, in a concerted manner that maintains the relative spatial orientations of transferred features.

Pattern Transfer Printing by Kinetic Control of Adhesion to an Elastomeric Stamp

We present results of ideal epitaxial nucleation and growth of III−V semiconductor nanowires on silicon substrates. This addresses the long-time challenge of integrating high performance III−V semiconductors with mainstream Si technology. Efficient room-temperature generation of light on silicon is demonstrated by the incorporation of double heterostructure segments in such nanowires. We expect that advanced heterostructure devices, such as resonant tunneling diodes, superlattice device structures, and heterostructure photonic devices for on-chip communication, could now become available as complementary device technologies for integration with silicon.

Epitaxial III-V nanowires on silicon

We demonstrate the use of nanoimprint lithography to define arrays of vertical InP nanowires. Each nanowire is individually seeded from a catalyzing gold particle and then grown via vapor-liquid-solid growth in a metal-organic vapor phase epitaxy system. The diameter and position of each nanowire can be controlled to create engineered arrays, demonstrated with a hexagonal photonic crystal pattern. This combination of nanoimprint and self-assembly of nanostructures is attractive for photonics and electronics, as well as in life sciences.

Nanowire Arrays Defined by Nanoimprint Lithography

Controlled growth of nanowires is an important, emerging research field with many applications in, for example, electronics, photonics, and life sciences. Nanowires of zinc blende crystal structure, grown in the 〈111〉B direction, which is the favoured direction of growth, usually have a large number of twin-plane defects. Such defects limit the performance of optoelectronic nanowire-based devices. To investigate this defect formation, we examine GaP nanowires grown by metal-organic vapour-phase epitaxy. We show that the nanowire segments between the twin planes are of octahedral shape and are terminated by {111} facets, resulting in a microfaceting of the nanowires. We discuss these findings in a nucleation context, where we present an idea on how the twin planes form. This investigation contributes to the understanding of defect formation in nanowires. One future prospect of such knowledge is to determine strategies on how to control the crystallinity of nanowires.

Structural properties of 〈111〉B -oriented III–V nanowires

We have synthesized GaAs−GaxIn1-xP (0.34 < x < 0.69) core−shell nanowires by metal−organic vapor phase epitaxy. The nanowire core was grown Au-catalyzed at a low temperature (450 °C) where only little growth takes place on the side facets. The shell was added by growth at a higher temperature (600 °C), where the kinetic hindrance of the side facet growth is overcome. Photoluminescence measurements on individual nanowires at 5 K showed that the emission efficiency increased by 2 to 3 orders of magnitude compared to uncapped samples. Strain effects on the band gap of lattice mismatched core−shell nanowires were studied and confirmed by calculations based on deformation potential theory.

Growth and Optical Properties of Strained GaAs−GaxIn1-xP Core−Shell Nanowires

We present a mass transport model based on surface diffusion for metal-particle-assisted nanowire growth. The model explains the common observation that for III/V materials thinner nanowires are longer than thicker ones. We have grown GaP nanowires by metal-organic vapor phase epitaxy and compared our model calculations with the experimental nanowire lengths and radii. Moreover, we demonstrate that the Gibbs-Thomson effect can be neglected for III/V nanowires grown at conventional temperatures and pressures.

Werner Seifert

Papers

Epitaxial III-V nanowires on silicon

Nanowire Arrays Defined by Nanoimprint Lithography

Structural properties of 〈111〉B -oriented III–V nanowires

Growth and Optical Properties of Strained GaAs−GaxIn1-xP Core−Shell Nanowires

Mass transport model for semiconductor nanowire growth.