A method using a generate-and-verify computer program product to generate by repetitive passes a design rules checking computer program, wherein the design rules are described in a file called a runset. The design rules checking program is used for exhaustive testing of VLSI chips for compliance to the design rules of a given VLSI fabrication process. The runset is repeatedly iterated in loop fashion with respect to a testcase file containing groups of layout structures or shapes used for verifying the correctness of the runset. A general purpose shapes processing program creates an error shapes file for storing geometrical errors found in each said layout structure. Two additional shapes are used in the verification process: user boundary shapes for defining areas in which errors are not to be detected for a given design rule, and automated boundary shapes created to surround each said layout structure with a boundary that defines regions where error shapes can occur. An association table is created which is a compilation of the error shapes, user boundary shapes, and automated boundary shapes associated with each layout structure. The association table is processed to determine the correctness of the runset. The runset is modified to correct each valid error. The repetitive passes continue until a final runset is generated. This final runset becomes the input to design rules checking computer program product and customizes the program for a given VLSI fabrication process.

Method for verifying design rule checking software

A semiconductor device includes a substrate and a number of diffusion regions defined within the substrate. The diffusion regions are separated from each other by a non-active region of the substrate. The semiconductor device includes a number of linear gate electrode tracks defined to extend over the substrate in a single common direction. Each linear gate electrode track is defined by one or more linear gate electrode segments. Each linear gate electrode track that extends over both a diffusion region and a non-active region of the substrate is defined to minimize a separation distance between ends of adjacent linear gate electrode segments within the linear gate electrode track, while ensuring adequate electrical isolation between the adjacent linear gate electrode segments.

Dynamic array architecture

A restricted layout region includes a diffusion level layout including p-type and n-type diffusion region layout shapes separated by a central inactive region. The diffusion region layout shapes are defined in a non-symmetrical manner relative to a centerline defined to bisect the diffusion level layout. A gate electrode level layout is defined to include linear-shaped layout features placed to extend in only a first parallel direction. Adjacent linear-shaped layout features that share a common line of extent in the first parallel direction are separated by an end-to-end spacing that is substantially equal across the gate electrode level layout and that is minimized to an extent allowed by a semiconductor device manufacturing capability. The gate electrode level layout includes linear-shaped layout features defined along at least four different lines of extent in the first parallel direction. The restricted layout region corresponds to an entire gate electrode level of a cell layout.

Semiconductor Device Layout Including Cell Layout Having Restricted Gate Electrode Level Layout with Linear Shaped Gate Electrode Layout Features Defined Along At Least Four Gate Electrode Tracks with Minimum End-to-End Spacing with Corresponding Non-Symmetric Diffusion Regions

A system and method for automatically creating testcases for design rule checking comprises first creating a table with a design rule number, a description, and the values from a design rule manual. Next, any design specific options are derived that affect the flow of the design rule checking, including back end of the line stack options. Then, the design rule values and any design specific options (including back end of the line stack options) are extracted into testcases. Next, the testcases are organized such that there is one library with a plurality of root cells, further comprising one root cell for checking all rules pertaining to the front end of the line, and another root cell for checking design specific options including back end of the line stack options. Finally, the DRC runset is run against the testcases to determine if the DRC runset provides for design rule checking.

Method for comprehensively verifying design rule checking runsets

A method is disclosed for defining a dynamic array section to be manufactured on a semiconductor chip. The method includes defining a peripheral boundary of the dynamic array section. The method also includes defining a manufacturing assurance halo outside the boundary of the dynamic array section. The method further includes controlling chip layout features within the manufacturing assurance halo to ensure that manufacturing of conductive features inside the boundary of the dynamic array section is not adversely affected by chip layout features within the manufacturing assurance halo.

Methods for Defining Dynamic Array Section with Manufacturing Assurance Halo and Apparatus Implementing the Same

According to the present embodiment, a method for calculating the parasitic capacitance in a semiconductor device is disclosed. According to the preferred method, a layout file containing the shapes of a semiconductor device is provided. The dimensions of the layout file are then adjusted to wafer dimensions so as reflect actual production devices. The shapes of the layout file are then partitioned into simpler shapes, typically abutted rectangles, called tiles. Each tile is then decomposed into overlap and fringe capacitance components, each component having a uniform capacitance environment with respect to its capacitance elements. The parasitic capacitance of the semiconductor device can thus be accurately computed, with an efficient use of resources. Additionally the preferred embodiment is easily adaptable to a wide range of technology types.

Method and apparatus for modeling capacitance in an integrated circuit

A system, method and program product for performing density checking of an IC design. The invention establishes an evaluation array for the IC design including an array element for each evaluation window of the IC design. The number of evaluation windows is based on a smallest necessary granularity. A single pass through shape data for the IC design is then conducted to populate each array element with a shape area for a corresponding evaluation window. Density checking is performed by iterating over the evaluation array using a sub-array. The sub-array may have the size of the preferred density design rule window. The invention removes the need for repetitive calculations, and results in a more efficient approach to density checking.

William F. DeCamp

Papers

Method for verifying design rule checking software

Method and apparatus for modeling capacitance in an integrated circuit

IC design density checking method, system and program product