P
Peter A. Habitz
Researcher at IBM
Publications - 78
Citations - 952
Peter A. Habitz is an academic researcher from IBM. The author has contributed to research in topics: Static timing analysis & Integrated circuit. The author has an hindex of 17, co-authored 78 publications receiving 945 citations.
Papers
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Proceedings ArticleDOI
Process and environmental variation impacts on ASIC timing
TL;DR: In this paper, the authors introduce the concepts of systematic interdie variation, systematic intra-die variation and intra die random variation and show that by treating these forms of variations differently, they can achieve design closure with less guard-banding than traditional methods.
Patent
Three dimensional track-based parasitic extraction
Laura R. Darden,James J. Engel,Peter A. Habitz,William J. Livingstone,Daniel Joseph Mainiero,Jeannie H. Panner,Michael Timothy Trick,Paul S. Zuchowski +7 more
TL;DR: In this article, the capacitance and resistance of each global wire on the chip, one wire at a time, are calculated by searching neighboring tracks within the surrounding cube for adjacent elements that could cause capacitive effects or affect the resistance of the wire.
Proceedings ArticleDOI
Variation-aware performance verification using at-speed structural test and statistical timing
Vikram Iyengar,Jinjun Xiong,Subbayyan Venkatesan,Vladimir Zolotov,David E. Lackey,Peter A. Habitz,Chandu Visweswariah +6 more
TL;DR: A novel variation-aware method based on statistical timing to select critical paths for structural test for performance verification in the presence of process variation is presented.
Patent
Method and apparatus for modeling capacitance in an integrated circuit
TL;DR: In this article, a method for calculating the parasitic capacitance in a semiconductor device is presented, where a layout file containing the shapes of the semiconductor devices is provided, and the dimensions of the layout file are then adjusted to wafer dimensions so as to reflect actual production devices.
Patent
Method and system for evaluating timing in an integrated circuit
TL;DR: In this paper, the authors propose methods for analyzing the timing in integrated circuits and for reducing the pessimism in timing slack calculations in static timing analysis, which involve grouping and canceling the delay contributions of elements having similar delays in early and late circuit paths.