This paper addresses optimal energy-efficient design for uplink (UL) MU-MIMO in a single cell environment. The energy efficiency is measured by throughput per Joule, while both RF transmission power and device electronic circuit power are considered. We define the energy efficiency (EE) capacity for UL MU-MIMO and study the power allocation that achieves this capacity. First we assume all users consume a fixed amount of circuit power and show that user antennas should be used only when the corresponding spatial channels are sufficiently good and using them improves the overall network EE. Mobile devices may have improved circuit management capability and turn off circuit operations when some antennas are not used to reduce circuit power consumption. Therefore we further study energy-efficient UL MU-MIMO with improved circuit management and show that some antennas should not be used even when their channel states are good because turning them on consumes too much circuit power. Based on theoretical analysis, we further develop low-complexity yet globally optimal energy-efficient power allocation algorithms that converge to the optimum exponentially. Simulation results are provided to demonstrate the significant gain in network energy efficiency.

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Energy-Efficient Uplink Multi-User MIMO

Recent trends of increasing core-count and memory/bandwidth-wall have led to major overhauls in chip architecture. In face of increasing cache capacity demands, researchers have now explored DRAM, which was conventionally considered synonymous to main memory, for designing large last level caches. Efficient integration of DRAM caches in mainstream computing systems, however, also presents several challenges and several recent techniques have been proposed to address them. In this paper, we present a survey of techniques for architecting DRAM caches. Also, by classifying these techniques across several dimensions, we underscore their similarities and differences. We believe that this paper will be very helpful to researchers for gaining insights into the potential, tradeoffs and challenges of DRAM caches.

A Survey Of Techniques for Architecting DRAM Caches

Sphere Decoding (SD) is a highly effective detection technique for Multiple-Input Multiple-Output (MIMO) wireless communications receivers, offering quasi-optimal accuracy with relatively low computational complexity as compared to the ideal ML detector. Despite this, the computational demands of even low-complexity SD variants, such as Fixed Complexity SD (FSD), remains such that implementation on modern software-defined network equipment is a highly challenging process, and indeed real-time solutions for MIMO systems such as 4 × 4 16-QAM 802.11n are unreported. This paper overcomes this barrier. By exploiting large-scale networks of fine-grained software-programmable processors on Field Programmable Gate Array (FPGA), a series of unique SD implementations are presented, culminating in the only single-chip, real-time quasi-optimal SD for 4 × 4 16-QAM 802.11n MIMO. Furthermore, it demonstrates that the high performance software-defined architectures which enable these implementations exhibit cost comparable to dedicated circuit architectures.

Software-Defined Sphere Decoding for FPGA-Based MIMO Detection

Covering the fundamental principles and state-of-the-art cross-layer techniques, this practical guide provides the tools needed to design MIMO- and OFDM-based wireless networks that are both energy- and spectrum-efficient. Technologies are introduced in parallel for both centralized and distributed wireless networks to give you a clear understanding of the similarities and differences between their energy- and spectrum-efficient designs, which is essential for achieving the highest network energy saving without losing performance. Cutting-edge green cellular network design technologies, enabling you to master resource management for next-generation wireless networks based on MIMO and OFDM, and detailed real-world implementation examples are provided to guide your engineering design in both theory and practice. Whether you are a graduate student, a researcher or a practitioner in industry, this is an invaluable guide.

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Energy and Spectrum Efficient Wireless Network Design

In this paper we describe three 3D standard cell placement algorithms, which are: “3D Placement using Sequential Off-the-Shelf 2D Placement Tools”, “True-3D Analytical Placement with mPL” and “3D Placement using Simultaneous 2D Placements with mPL”. We use these algorithms to place three case studies in a real face-to-face 3D integration process. The three case studies are a 2 point FFT butterfly processing element (PE), an Advanced Encryption Standard encryption block (AES) and a multiple-input and multiple-output wireless decoder (MIMO). The placements are then fully routed and compared to 2D placements in terms of performance and power consumption. Using this methodology we show that using 3D face-to-face integration with microbumps in conjunction with the three placement algorithms we can improve the maximum clock speed of AES module by 15.3% and the PE by 22.6%, while reducing the power of the AES module and the PE by 2.6% and 12.9% respectively.

Logic-on-logic 3D integration and placement

MIMO wireless technology is required to increase the data rates for a broad range of applications, including low cost mobile devices. In this paper we present a very low area reconfigurable MIMO detector which achieves a high throughput of 103Mbps and uses 27 Kilo Gates when implemented in a commercial 180nm CMOS process. The low area is achieved by the proposed in-place architecture. This architecture implements the K-best algorithm and reduces area 4-fold compared to the widely used multi-stage architecture, while provides reconfigurability in terms of antenna configuration during real-time operation.

A low-area flexible MIMO detector for WiFi/WiMAX standards

A parallel merge algorithm is proposed that results in a smaller critical-path delay than all of the other merge algorithms explored. The parallel merge circuit effectively increases the throughput of VLSI signal processing systems. The critical path of this circuit is independent of the number of input values.

Parallel merge algorithm for high-throughput signal processing applications

Sphere Decoders (SD) have found more popularity among other MIMO detectors because of their close-to-ML error-rate performance and lower hardware complexity. One of the variants of SD is the K-best algorithm. The conventional implementations of K-best are not fast enough to be considered for hardware implementation of the emerging standards like 802.11n because of the throughput bottleneck which is the sort operation. In this work we have proposed the parallel merge algorithm (PMA), which enables us to use more pipeline levels in the system because of its short critical path, resulting in throughput increase, about 4 times compared to the other K-best implementations. Also, we have modified the K-best algorithm by discarding the calculation of unnecessary paths ,which results in a 20% decrease in area and 44% decrease in the number of operations compared to the original K-best.

High-throughput low-complexity MIMO detector based on K-best algorithm

A power/area aware design is mandatory for the MIMO (Multi-Input Multi-Output) detectors used in LTE and WiMAX standards The 64-QAM modulation used in the MIMO detector requires more detection effort compared to the smaller constellation sizes widely implemented in the literature In this work we propose a new architecture for the K-best detector, which unlike the popular multi-stage architecture used for K-best detectors, implements just one core Also, we introduce a slight modification to the K-best algorithm that reduces the number of multiplications by 44%, and reduces the total power consumption by 27%, without any noticeable performance degradation The overall architecture consumes only 24KGate, which is the smallest area compared to the other implementations in the literature It also results in an at least 4-fold greater throughput-efficiency (Mbps/KiloGate) compared to the other detectors, while consuming a small power The decoder implemented in a commercial 130nm process provides a data-rate of 107Mbps, and consumes 544mW

An energy-efficient 64-QAM MIMO detector for emerging wireless standards

In this paper, we present novel techniques to handle the complexity and challenges in clock distribution for 3-D integrated circuit. First, we propose a novel active deskew technique to adaptively mitigate the cross-tier variations and the 3-D wiring asymmetry. The new deskew technique neither relies on an accurate through-silicon-vias model nor an accurate reference clock distribution. Second, we design a phase-mixer-based tunable-delay-buffer (TDB), which can be linearly tuned in 360° and tolerant to process-voltage-termperature (PVT) variations. Third, based on the new deskew technique and TDB design, we propose an efficient clock distribution network topology, which can be realized without a need of balanced H-tree. Moreover, a thermal profile-based optimization flow is developed to further improve the power efficiency and reduce design overhead. A case study shows that the proposed techniques are able to largely improve the clock skews. The optimization flow is capable of reducing the design cost to achieve a better tradeoff of the skew performance and the design overhead.

William Rhett Davis

Papers

A low-area flexible MIMO detector for WiFi/WiMAX standards

Parallel merge algorithm for high-throughput signal processing applications

High-throughput low-complexity MIMO detector based on K-best algorithm

An energy-efficient 64-QAM MIMO detector for emerging wireless standards

Adaptive and Reliable Clock Distribution Design for 3-D Integrated Circuits