Showing papers by "Wolfgang Fichtner published in 1995"

A technology oriented model for transient diffusion and activation of boron in silicon

Abstract: We propose a model for point‐defect‐assisted transient diffusion and activation of high‐dose boron implants in silicon. To model transient diffusion, a nonlinear equilibrium clustering model for point defects is used. The activation of boron is modeled as a Fermi‐level‐dependent transformation of inactive dopant clusters to substitutional atoms. Comparison with experimental data shows that this approach can provide a description of both rapid thermal annealing and long‐time furnace annealing steps, with an excellent predictive capability for both chemical and electrically active profiles.

Punch-through IGBTs with homogeneous n-base operating at 4 kV line voltage

Abstract: Insulated Gate Bipolar Transistors (IGBTs) for snubberless operation at 4 kV line voltage in inductively loaded circuits have been developed, fabricated and characterized. The key point in the development of these high voltage devices is the Punch-Through (PT) structure which makes use of homogeneous wafer material for the n-base layer combined with a buffer layer diffused from the backside instead of double epitaxial material conventionally used in PT structures. The anode is equipped with emitter shorts to reduce the switching losses. The on-state voltage of the IGBTs is between 2.2 V and 3.4 V at 100 A cm/sup -2/ dependent on the buffer layer implant dose. The leakage current of these devices is less than 8/spl middot/10/sup -6/ A cm/sup -2/ at 5 kV blocking voltage and at room temperature. It was demonstrated that these IGBTs are able to turn off a current density of 50 A cm/sup -2/ at a line voltage of 4 kV in about 5 /spl mu/s under inductive load without any snubber, thereby producing a turn-off energy density of 220 mJ cm/sup -2/.

Layout optimization of an ESD-protection n-MOSFET by simulation and measurement

Abstract: This paper presents a new method for optimizing the performance of a lateral npn-transistor used as ESD protection element. Relying on process modeling and thermo-electrical device simulations we are able to use device-internal quantities such as the electric field or the temperature distribution to find the optimal transistor layout. Guided by simulation we are able to guarantee that the avalanche breakdown propagates properly along a single meander-like collector junction. Experimental result from measurements show that this is crucial for better ESD performance of a space efficient device. Our optimized device reaches 83% of the second breakdown trigger current of a straight device. Compared to a unoptimized meander-like device we could increase its performance by 63%. The good agreement between measurements and simulation for different shapes of transistors validates our methodology and approach to optimization of ESD devices.

On-state and short circuit behaviour of high voltage trench gate IGBTs in comparison with planar IGBTs

Abstract: The impact of the cathode geometry on conduction and switching properties of high voltage trench gate IGBTs is analysed using mixed mode two-dimensional device and circuit simulation tools. The most effective means to minimize conduction losses by injection enhancement at the cathode is the reduction of the width of the mesa containing n/sup +/ electron emitters and the MOS channel regions. As compared to planar IGBTs, the improvement is most pronounced at higher operating temperatures. If low short circuit current densities are of concern, optimized trench gate geometries also require wide trenches. Trading off conduction losses against turn-off losses, trench gate IGBTs generate approximately 30 to 40% less turn-off losses as planar IGBTs with identical on-state voltage.

Full three-dimensional numerical analysis of multi-collector magnetotransistors with directional sensitivity

Abstract: We have studied the operation of multi-collector bipolar transistors with directional magnetic-field sensitivity. The complex three-dimensional (3D) device consists of four crosswise-arranged lateral transistors with one common central emitter. To analyse the electrical characteristics and sensor performance, we have modelled the complete device structure using technological and physical parameters extracted from experimental measurements on real devices. Because of the complex geometry, a full 3D numerical analysis of carrier flow and electrostatic potential is required in order to study the effects of an arbitrarily oriented magnetic field. A simplified analysis confined to the 2D central mirror plane is inadequate even for the mere electric device behaviour at zero magnetic field. This reflects the problem of current calibration inherent in 2D approximations of devices with widely differing contact areas. To overcome this discrepancy, we have implemented for the first time the 3D galvanomagnetic transport vector equations in a state-of-the-art general-purpose device simulator.

A comparison of emitter concepts for high voltage IGBTs

Abstract: The impact of the injection efficiency of unshorted anode p/sup +/emitters on the static and dynamic electrical characteristics of high voltage non-punchthrough IGBTs is analysed using mixed mode two-dimensional device and circuit simulation tools. The results are compared to IGBT device structures with shorted anodes. IGBTs with high and low efficiency anode emitters can be designed to have the same conduction losses despite major differences in the p/sup +/emitter doping profiles and the carrier lifetime. Turn-off losses are in general higher for IGBTs with homogeneous low efficiency emitters. Pushing the trade-off between conduction and turn-off losses to the level set by anode shorted IGBTs is also feasible for homogeneous, low efficiency p/sup +/emitter devices, though it requires approaching the technological limits of injection efficiency and carrier lifetime.

Unified Grid Generation and Adaptation for Device Simulation

Abstract: This paper describes the design and development of a dimension-independent grid generator suitable for device simulation. The purpose of this work is to describe a modular, flexible and dimension-independent approach for the generation of grids with complex boundary restrictions.

Multi-Dimensional TCAD: The PROMPT/DESSIS Approach

Abstract: Designing new semiconductor devices for very large scale integrated circuits (VLSI) requires intensive use of process and device simulation tools to reduce development costs. However, valid device simulation results can only be achieved when a high geometrical modeling precision has been reached during the process simulation phase. Accurate finite element simulators embedded in a multi-dimensional process simulation environment help to fulfill this quality requirement. Since general-purpose three-dimensional (3D) process simulators are not yet available, a modern design environment combines solid modeling techniques with one-dimensional (1D) and two-dimensional (2D) finite element simulators. In this article we present a consistent and integrated process simulation environment that eases the characterization and optimization of semiconductor devices. The straightforward modeling in all three dimensions of an EEPROM cell illustrates the presented approach.

Full-Band Monte Carlo Transport Calculation in an Integrated Simulation Platform

Abstract: We present a hierarchical CAD environment for realistic silicon device simulation, combining the utility of process, drift-diffusion/hydrodynamic, and Monte Carlo simulation in a unified platform Monte Carlo simulation results are presented for the cases of an NIN diode and a 40nm LDD-MOSFET, using information given by a hydrodynamic pre-processing step In addition we compare drift-diffusion, hydrodynamic and Monte Carlo results for an 05µm MOSFET whose geometry and doping profiles were generated by a 2-dimensional process simulation

Precipitation phenomena and transient diffusion/activation during high concentration boron annealing

Abstract: The understanding of low thermal budget transient diffusion and activation of shallow p+ implants remains a crucial issue of technology simulation. In this paper, we apply a coupled point defect assisted diffusion/precipitation model to the redistribution phenomena observed during annealing of shallow boron implants. Comparison with experimental data shows that the precipitation model can account for unusual segregation phenomena in the highly disordered zone around the projected range of the as-implanted profile.

Large Scale Thermal Mixed Mode Device and Circuit Simulation

Abstract: The thermal mixed-mode capabilities of the device and circuit simulator Dessis are presented. The mode allows both electrical and thermal netlists to interconnect physical and circuit devices. As an example, the full electrothermal simulation of IGBT power module is presented.

An Approach for Explaining Drift Phenomena in GTO Devices Using Numerical Device Simulation

Abstract: A possible cause for IGT drift in GTO thyristors has been identified using numerical 2D device simulation. An increase of the surface recombination velocity under the oxide between the gate and cathode contacts leads to a small degradation of the upper npn transistor gain, which in turn rises the IGT. This work focuses on the requirements on the geometrical discretization and on the procedure to extract the DC current gains of the individual transistors that form the GTO thyristor.

New generation MOS controlled power devices and their applications

Abstract: Power integrated circuits and devices are at the heart of many system applications ranging from more or less conventional analog circuits operated at non-standard voltage levels to complex systems composed of parallel arrangements of multi-layer devices such as MOSFETs, bipolar transistors and thyristor devices. Driven by the rapid advances in device technology and the demands for new, more efficient electronic systems, new generations of MOS controlled power devices are entering the market place. This is true even for very high voltage applications, where the once secure position of the Gate-Turn-Off Thyristor (GTO) is being challenged today by new MOS-controlled switch elements such as the Insulated Gate Bipolar Transistor (IGBT).