https://www.iue.tuwien.ac.at/pdf/ib_2011/JB2011_Grasser_5.pdf

Stochastic charge trapping in oxides: From random telegraph noise to bias temperature instabilities

One of the most important degradation modes in CMOS technologies, the bias temperature instability (BTI) has been known since the 1960s. Already in early interpretations, charge trapping in the oxide was considered an important aspect of the degradation. In their 1977 paper, Jeppson and Svensson suggested a hydrogen-diffusion controlled mechanism for the creation of interface states. Their reaction-diffusion model subsequently became the dominant explanation of the phenomenon. While Jeppson and Svensson gave a preliminary study of the recovery of the degradation, this issue received only limited attention for many years. In the last decade, however, a large number of detailed recovery studies have been published, showing clearly that the reaction-diffusion mechanism is inconsistent with the data. As a consequence, the research focus shifted back toward charge trapping. Currently available advanced charge-trapping theories based on switching oxide traps are now able to explain the bulk of the experimental data. We give a review of our perspective on some selected developments in this area.

The Paradigm Shift in Understanding the Bias Temperature Instability: From Reaction–Diffusion to Switching Oxide Traps

Precise measurement of digital circuit degradation is a key aspect of aging tolerant digital circuit design. In this study, we present a fully digital on-chip reliability monitor for high-resolution frequency degradation measurements of digital circuits. The proposed technique measures the beat frequency of two ring oscillators, one stressed and the other unstressed, to achieve 50 X higher delay sensing resolution than that of prior techniques. The differential frequency measurement technique also eliminates the effect of common-mode environmental variation such as temperature drifts between each sampling points. A 265 X 132 mum2test chip implementing this design has been fabricated in a 1.2 V, 130 nm CMOS technology. The measured resolution of the proposed monitoring circuit was 0.02%, as the ring oscillator in this design has a period of 4 ns; this translates to a temporal resolution of 0.8 ps. The 2 mus measurement time was sufficiently short to suppress the unwanted recovery effect from concealing the actual circuit degradation.

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Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits

The similarity between Random Telegraph Noise and Negative Bias Temperature Instability (NBTI) relaxation is further demonstrated by the observation of exponentially-distributed threshold voltage shifts corresponding to single-carrier discharges in NBTI transients in deeply scaled pFETs. A SPICE-based simplified channel percolation model is devised to confirm this behavior. The overall device-to-device ΔV th distribution following NBTI stress is argued to be a convolution of exponential distributions of uncorrelated individual charged defects Poisson-distributed in number. An analytical description of the total NBTI threshold voltage shift distribution is derived, allowing, among other things, linking its first two moments with the average number of defects per device.

Origin of NBTI variability in deeply scaled pFETs

Negative-bias-temperature instability (NBTI) has become the primary limiting factor of circuit life time. In this paper, we develop a hierarchical framework for analyzing the impact of NBTI on the performance of logic circuits under various operation conditions, such as the supply voltage, temperature, and node switching activity. Given a circuit topology and input switching activity, we propose an efficient method to predict the degradation of circuit speed over a long period of time. The effectiveness of our method is comprehensively demonstrated with the International Symposium on Circuits and Systems (ISCAS) benchmarks and a 65-nm industrial design. Furthermore, we extract the following key design insights for reliable circuit design under NBTI effect, including: 1) During dynamic operation, NBTI-induced degradation is relatively insensitive to supply voltage, but strongly dependent on temperature; 2) There is an optimum supply voltage that leads to the minimum of circuit performance degradation; circuit degradation rate actually goes up if supply voltage is lower than the optimum value; 3) Circuit performance degradation due to NBTI is highly sensitive to input vectors. The difference in delay degradation is up to 5× for various static and dynamic operations. Finally, we examine the interaction between NBTI effect, and process and design uncertainty in realistic conditions.

The Impact of NBTI Effect on Combinational Circuit: Modeling, Simulation, and Analysis

We present a new direct VT measurement technique with arbitrary choice of drain voltage and a mus delay (factor of 1000 improvement) after stress. As shown this technique enables a meaningful comparison of data to theory (e.g. DeltaVT measurable as response to stress times from 100mus over 10 decades in time and an analysis of recovery over 11 decades in time) which may lead to a better understanding of NBTI. A fast precursor due to bulk trapping was found to significantly influence degradation slopes for all times. Based on a physical model - standard reaction/diffusion model plus fast bulk trapping -with just 3 fit parameters experimental degradation can be well modelled and degradation slopes frac14 (both reported in literature) can be explained. A lifetime extrapolation based on this physical model is superior to the common straight line fit. There is no satisfying agreement of recovery data with reaction/diffusion theory. Further experimental and theoretical work is going to be needed

Analysis of NBTI Degradation- and Recovery-Behavior Based on Ultra Fast VT-Measurements

The physical origin of the Negative Bias Temperature Instability (NBTI) is still under debate. In this work we analyze the single defects constituting NBTI. We introduce a new measurement technique stimulating a charging of these defects. By employing a statistical analysis of many stochastic stimulation processes of the same defect we are able to determine the electric field and the temperature dependence of these defects with great precision. Based on our experiments we present and verify a new, physics-based, quantitative model allowing a precise prediction of NBTI degradation and recovery. This model takes the stress history into account and also provides a prediction for degradation due to AC-NBTI and an understanding of the special features seen in conjunction with AC-NBTI.

The statistical analysis of individual defects constituting NBTI and its implications for modeling DC- and AC-stress

Measuring the degradation of modern devices subjected to bias temperature stress has turned out to be a formidable challenge. Interestingly, measurement techniques such as fast- Vth, on-the-fly ID,lin, and charge-pumping give quite different results. This has often been explained by the inherent recovery in non-on-the-fly techniques. Still, all these techniques deliver important information on the degradation and recovery behavior and a rigorous understanding linking these results is still missing. Based on our detailed studies of the recovery, we propose a new measurement technique which allows the simultaneous extraction of two distinctly different components, a fast universally recovering component and a slow, nearly permanent component.

/pdf/simultaneous-extraction-of-recoverable-and-permanent-1cujx2du5o.pdf

Simultaneous Extraction of Recoverable and Permanent Components Contributing to Bias-Temperature Instability

An overview over issues and findings in SiC power MOSFET reliability is given. The focus of this article is on threshold instabilities and the differences to Si power MOSFETs. Measurement techniques for the characterization of the threshold voltage instabilities are compared and discussed. Modeling of the threshold voltage instabilities based on capture–emission-time (CET) maps is a central topic. This modeling approach takes the complete gate bias/temperature history into account. It includes both gate stress polarities and is able to reproduce the short-term threshold variations during application-relevant 50-kHz bipolar ac-stress. In addition, the impact on circuit operation is discussed.

Review on SiC MOSFETs High-Voltage Device Reliability Focusing on Threshold Voltage Instability

We present a model for AC NBTI which is based on capture and emission of charges in and out of oxide border traps. Capture and emission time constants of these traps are widely distributed from &#60;µs to >105s and have been experimentally determined. The model gives a good quantitative understanding of experimental data from alternating stress / recovery sequences. It also provides a physical understanding of all the special features seen in AC NBTI independently of technology parameters.

Wolfgang Gustin

Papers

Analysis of NBTI Degradation- and Recovery-Behavior Based on Ultra Fast VT-Measurements

The statistical analysis of individual defects constituting NBTI and its implications for modeling DC- and AC-stress

Simultaneous Extraction of Recoverable and Permanent Components Contributing to Bias-Temperature Instability

Review on SiC MOSFETs High-Voltage Device Reliability Focusing on Threshold Voltage Instability

Understanding and modeling AC BTI