The phase-shifting mask consists of a normal transmission mask that has been coated with a transparent layer patterned to ensure that the optical phases of nearest apertures are opposite. Destructive interference between waves from adjacent apertures cancels some diffraction effects and increases the spatial resolution with which such patterns can be projected. A simple theory predicts a near doubling of resolution for illumination with partial incoherence σ < 0.3, and substantial improvements in resolution for σ < 0.7. Initial results obtained with a phase-shifting mask patterned with typical device structures by electron-beam lithography and exposed using a Mann 4800 10× tool reveals a 40-percent increase in usuable resolution with some structures printed at a resolution of 1000 lines/mm. Phase-shifting mask structures can be used to facilitate proximity printing with larger gaps between mask and wafer. Theory indicates that the increase in resolution is accompanied by a minimal decrease in depth of focus. Thus the phase-shifting mask may be the most desirable device for enhancing optical lithography resolution in the VLSI/VHSIC era.

Improving resolution in photolithography with a phase-shifting mask

The field of plasma etching is reviewed. Plasma etching, a revolutionary extension of the technique of physical sputtering, was introduced to integrated circuit manufacturing as early as the mid 1960s and more widely in the early 1970s, in an effort to reduce liquid waste disposal in manufacturing and achieve selectivities that were difficult to obtain with wet chemistry. Quickly, the ability to anisotropically etch silicon, aluminum, and silicon dioxide in plasmas became the breakthrough that allowed the features in integrated circuits to continue to shrink over the next 40 years. Some of this early history is reviewed, and a discussion of the evolution in plasma reactor design is included. Some basic principles related to plasma etching such as evaporation rates and Langmuir–Hinshelwood adsorption are introduced. Etching mechanisms of selected materials, silicon, silicon dioxide, and low dielectric-constant materials are discussed in detail. A detailed treatment is presented of applications in current silicon integrated circuit fabrication. Finally, some predictions are offered for future needs and advances in plasma etching for silicon and nonsilicon-based devices.

/pdf/plasma-etching-yesterday-today-and-tomorrow-4a8eftp390.pdf

Plasma etching: Yesterday, today, and tomorrow

The design of airport queuing networks is a significant research field currently for researchers. Many factors must to be considered in order to achieve the optimized strategies, including the passenger flow volume, boarding time, and boarding order of passengers. Optimizing these factors lead to the sustainable development of the queuing network, which currently faces a few difficulties. In particular, the high variance in checkpoint lines can be extremely costly to passengers as they arrive unduly early or possibly miss their scheduled flights. In this article, the Monte Carlo method is used to design the queuing network so as to achieve sustainable development. Thereafter, a network diagram is used to determine the critical working point, and design a structurally and functionally sustainable network. Finally, a case study for a sustainable queuing-network design in the airport is conducted to verify the efficiency of the proposed model. Specifically, three sustainable queuing-network design solutions are proposed, all of which not only maintain the same standards of security, but also increase checkpoint throughput and reduce passenger waiting time variance.

Sustainable Queuing-Network Design for Airport Security Based on the Monte Carlo Method

Atomic layer etching (ALE) is a technique for removing thin layers of material using sequential reaction steps that are self-limiting. ALE has been studied in the laboratory for more than 25 years. Today, it is being driven by the semiconductor industry as an alternative to continuous etching and is viewed as an essential counterpart to atomic layer deposition. As we enter the era of atomic-scale dimensions, there is need to unify the ALE field through increased effectiveness of collaboration between academia and industry, and to help enable the transition from lab to fab. With this in mind, this article provides defining criteria for ALE, along with clarification of some of the terminology and assumptions of this field. To increase understanding of the process, the mechanistic understanding is described for the silicon ALE case study, including the advantages of plasma-assisted processing. A historical overview spanning more than 25 years is provided for silicon, as well as ALE studies on oxides, III–V compounds, and other materials. Together, these processes encompass a variety of implementations, all following the same ALE principles. While the focus is on directional etching, isotropic ALE is also included. As part of this review, the authors also address the role of power pulsing as a predecessor to ALE and examine the outlook of ALE in the manufacturing of advanced semiconductor devices.

https://avs.scitation.org/doi/pdf/10.1116/1.4913379

Overview of atomic layer etching in the semiconductor industry

Extreme ultraviolet lithography (EUVL) was thoroughly reviewed over a broad range of topics, including history, tools, source, metrology, condenser and projection optics, resists, and masks. Since 1988, many studies on EUVL have been conducted in North America, Europe, and Japan, through state sponsored programs and industrial consortiums. To date, no “show stopper” has been identified, but challenges are present in almost all aspects of EUVL technology. Commercial alpha lithography step-and-scan tools are installed with full-field capability; however, EUVL power at intermediate focus (IF) has not yet met volume manufacturing requirements. Compared with the target of 180W IF power, current tools can supply only approximately 55–62W. EUV IF power has been improved gradually from xenon- to tin-discharge-produced plasma or laser-produced plasma. EUVL resist has improved significantly in the last few years, with 25nm 1:1 line/space resolution being produced with approximately 2.7nm (3σ) line edge roughness. A...

Extreme ultraviolet lithography: A review

ArF lithography is essential to develop a sub-100 nm device, however, line edge roughness (LER) and line width roughness (LWR) is playing a critical role due to the immaturity of photoresist and the lack of etch resistance. Researchers are trying to improve LER/LWR properties by optimizing photoresist materials and process conditions. In this paper, experiment results are presented to study the impact of LER/LWR to device performance so that the reasonable control range of LER/LWR can be defined. To implement the experiment, 80 nm node of single NMOS transistors were fabricated, which had various range of gate length, width, and LER/LWR. The amount of LER/LWR could be successfully controlled by applying different resist materials, defocus, and over etch time. Experimental results show that leakage current is significantly increased when LWR is greater than 10 nm. In addition, it is observed that both threshold voltage and on-off current variation get increased exponentially as gate width decreases.

Effect of line-edge roughness (LER) and line-width roughness (LWR) on sub-100-nm device performance

We report optical characteristics of linear graded InxGa1−xAs (XIn=0–0.58) buffer layers grown on GaAs by low‐pressure metalorganic chemical vapor deposition. Two types of wirelike surface structures were observed from the layers grown at two different temperatures. Low‐temperature photoluminescence (PL) and double‐crystal x‐ray diffractometric measurements indicate that the PL energy and the relaxation of the graded layers were strongly dependent on the top surface structure. InGaAs cap layers were grown on top of the graded buffer layers with a variation of indium composition. A strong PL signal was observed from the top region of the graded layer grown with a lattice‐matched cap layer. It suggests that the top region of the grade, similar to a graded well structure, is compressively strained but is of high structural quality without dislocations.

Optical properties of InGaAs linear graded buffer layers on GaAs grown by metalorganic chemical vapor deposition

Synchronous pulse operation upon both source and bias RFs for inductively coupled plasma (ICP) etching system, having both dynamic matching networks and RF frequency-sweeping to ensure the lowest RF reflected power, is introduced for the first time. A superior performance of synchronous pulse operation to conventional continuous wave (cw) as well as source pulse operations is confirmed through plasma diagnostics by using Langmuir probe, plasma simulation by using hybrid plasma equipment model (HPEM) and etching performance. Significant reduction of RF power reflection during pulse operation as well as improvement of 35 nm gate critical dimension (CD) uniformity for sub-50 nm dynamic random access memory (DRAM) are achieved by adapting synchronous pulse plasma etching technology. It is definitely expected that synchronous pulse plasma system would have a great ability from a perspective of robustness on fabrication site, excellent gate CD controllability and minimization of plasma induced damage (PID) related device performance degradation.

Synchronous Pulse Plasma Operation upon Source and Bias Radio Frequencys for Inductively Coupled Plasma for Highly Reliable Gate Etching Technology

A mask for use in measuring flare produced by a projection lens of a photolithography system, a method of manufacturing the mask, a method of identifying a flare-affected region on a wafer, and a method for correcting for the flare to produce photoresist patterns of desired line widths are provided. A first photolithographic process is performed to form photoresist patterns on a test wafer using a mask including a light shielding region having a plurality of light transmission patterns and a light transmission region, and the photoresist patterns formed by light passing through the light transmission patterns of the light shielding region are compared to the photoresist patterns formed by light passing through the light transmission region. The amount of flare produced by the projection lens is quantified using the results of the comparison, and thus it is possible to identify a flare-affected region on the wafer. In addition, it is possible to form uniform photoresist patterns on the wafer by determining the open ratio of the flare-affected region and calculating an effective amount of the flare in the flare-affected region from the amount of flare of the lens and the open ratio. More specifically, a mask is produced in which the line widths of mask patterns are configured, i.e., corrected compared to the first mask, taking into consideration the effective amount of the flare.

Mask for use in measuring flare, method of manufacturing the mask, method of identifying flare-affected region on wafer, and method of designing new mask to correct for flare

A method for forming a pattern where the processing is simplified by using a silylated photoresist film, having retained the resolution increasing effect according to a multi-layer photoresist film process is disclosed, wherein a first photoresist layer (21) is formed on substrate (20) and part of the surface of the substrate is silylated, to thereby form a silylation layer (23). Then, a second photoresist layer (24) is formed on silylation layer (23), which then is exposed through the photo mask (25) having a predetermined pattern. Then, a second photoresist pattern (24a) is formed after development. Then, a silylation layer pattern (23a) is formed by etching-back the silylation layer (23) using the second photoresist pattern as (24a) an etching mask. Then, the silylation pattern (23a) is oxidized. and the first photoresist layer (21) is etched using the oxidized silylation pattern, thereby forming a first photoresist pattern (21a). A resolution increasing effect can be maintained only through the two layer photoresist film structure without the intermediate oxide film, while the process is simplified and the undesired polymer is less generated.

Woo-Sung Han

Papers

Effect of line-edge roughness (LER) and line-width roughness (LWR) on sub-100-nm device performance

Optical properties of InGaAs linear graded buffer layers on GaAs grown by metalorganic chemical vapor deposition

Synchronous Pulse Plasma Operation upon Source and Bias Radio Frequencys for Inductively Coupled Plasma for Highly Reliable Gate Etching Technology

Mask for use in measuring flare, method of manufacturing the mask, method of identifying flare-affected region on wafer, and method of designing new mask to correct for flare

Method for forming a pattern by silylation