W
Woorham Bae
Researcher at University of California, Berkeley
Publications - 64
Citations - 688
Woorham Bae is an academic researcher from University of California, Berkeley. The author has contributed to research in topics: CMOS & Phase-locked loop. The author has an hindex of 11, co-authored 64 publications receiving 466 citations. Previous affiliations of Woorham Bae include Seoul National University.
Papers
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Journal ArticleDOI
A 7.6 mW, 414 fs RMS-Jitter 10 GHz Phase-Locked Loop for a 40 Gb/s Serial Link Transmitter Based on a Two-Stage Ring Oscillator in 65 nm CMOS
TL;DR: A two-stage ring oscillator is used to provide a four-phase, 10 GHz clock for a quarter-rate TX, using a tri-state-inverter-based frequency-divider and an AC-coupled clock-buffer for high-speed operations with minimal power and area overheads.
Journal ArticleDOI
A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process
Sang-Hyeok Chu,Woorham Bae,Gyu-Seob Jeong,Sungchun Jang,Sungwoo Kim,Jiho Joo,Gyungock Kim,Deog-Kyoon Jeong +7 more
TL;DR: This paper presents a 22 to 26.5 Gb/s optical receiver with an all-digital clock and data recovery (AD-CDR) fabricated in a 65 nm CMOS process and employs an LC quadrature digitally controlled oscillator to achieve a high phase noise figure-of-merit at tens of gigahertz.
Journal ArticleDOI
Double‐Layer‐Stacked One Diode‐One Resistive Switching Memory Crossbar Array with an Extremely High Rectification Ratio of 109
Kyung Jean Yoon,Gun Hwan Kim,Sijung Yoo,Woorham Bae,Jung Ho Yoon,Tae Hyung Park,Dae Eun Kwon,Yeong Jae Kwon,Hae Jin Kim,Yu Min Kim,Cheol Seong Hwang +10 more
TL;DR: In this paper, a double-layer-stacked 1 diode-1 resistor (1D1R) cross-bar array (CBA) resistance switching random access memory is fabricated.
Proceedings ArticleDOI
An Error-free 1 Tbps WDM Optical I/O Chiplet and Multi-wavelength Multi-port Laser
Mark T. Wade,Erik Anderson,Shahab Ardalan,Woorham Bae,Behrooz Beheshtian,Sidney Buchbinder,K. Chang,P. Chao,H. Eachempatti,J. Frey,E. Jan,Austin Katzin,Anatoly Khilo,Derek M. Kita,U. Krishnamoorthy,Chen Li,Haiwei Lu,F. Luna,C. Madden,L. Okada,M. Patel,Chandarasekaran Ramamurthy,Manan Raval,R. Roucka,K. Robberson,Michael Rust,D. Van Orden,R. Zeng,Mason Zhang,Vladimir Stojanovic,Forrest Sedgwick,Roy Meade,N. Chan,John M. Fini,Byungchae Kim,Songtao Liu,Chong Zhang,Daniel Jeong,Pavan Bhargava,M. Sysak,Chen Sun +40 more
TL;DR: This work demonstrates 128 Gbps/port natively error-free transmission across eight optical ports using a 8-port, 8-λ/port WDM remote laser source and a pair of monolithically integrated CMOS optical I/O chiplets with 4.96-5.56 pJ/bit optical Tx+Rx chiplet energy efficiency.
Journal ArticleDOI
Comprehensive Writing Margin Analysis and its Application to Stacked one Diode‐One Memory Device for High‐Density Crossbar Resistance Switching Random Access Memory
TL;DR: In this article, it was shown that an additional voltage drop on the wire resistances of selected word and bit lines causes an increase in voltage for the write operation (programming/erasing), whose degree is associated with the selectivity of the RRAM selector, array size, resistance of the selected cell, and wire resistance.