An imaging device formed as a monolithic complementary metal oxide semiconductor integrated circuit in an industry standard complementary metal oxide semiconductor process, the integrated circuit including a focal plane array of pixel cells, each one of the cells including a photogate overlying the substrate for accumulating photo-generated charge in an underlying portion of the substrate, a readout circuit including at least an output field effect transistor formed in the substrate, and a charge coupled device section formed on the substrate adjacent the photogate having a sensing node connected to the output transistor and at least one charge coupled device stage for transferring charge from the underlying portion of the substrate to the sensing node.

/pdf/active-pixel-sensor-with-intra-pixel-charge-transfer-387ug1605r.pdf

Active pixel sensor with intra-pixel charge transfer

Single substrate device is formed to have an image acquistition device and a controller. The controller on the substrate controls the system operation.

/pdf/cmos-active-pixel-sensor-type-imaging-system-on-a-chip-1pw7w4xxhm.pdf

CMOS active pixel sensor type imaging system on a chip

The dielectric breakdown of ultra-thin 3 nm and 4 nm SiO/sub 2/ layers used as a gate dielectric in poly-Si gate capacitors is investigated. The ultra-thin gate oxide reliability was determined using tunnel current injection stressing measurements. A soft breakdown mechanism is demonstrated for these ultra-thin gate oxide layers. The soft breakdown phenomenon corresponds with an anomalous increase of the stress induced leakage current and the occurrence of fluctuations in the current. The soft breakdown phenomenon is explained by the decrease of the applied power during the stressing for thinner oxides so that thermal effects are avoided during the breakdown of the ultra-thin oxide capacitor. It is proposed that multiple tunnelling via generated electron traps in the ultra-thin gate oxide layer is the physical mechanism of the electron transport after soft breakdown. The statistical distributions of the charge to dielectric breakdown and to soft breakdown for a constant current stress of the ultra-thin oxides are compared. It is shown that for accurate ultra-thin gate oxide reliability measurements it is necessary to take the soft breakdown phenomenon into account.

Soft breakdown of ultra-thin gate oxide layers

Reliability issues for flash electrically erasable programmable read-only memories are reviewed. The reliability of both the source-erase type (ETOX) flash memory and the NAND structure EEPROM are discussed. Disturbs during programming, write/erase endurance, charge loss of both devices are reviewed, and the reliability of the tunnel oxide and the interpoly dielectric are described. It is shown that bipolarity F-N programming/erase, which is used in the NAND EEPROM, improves the charge to breakdown and decreases the stress-induced leakage current. >

/pdf/reliability-issues-of-flash-memory-cells-cnmfabakhy.pdf

Reliability issues of flash memory cells

Increases in pre-tunneling leakage currents in thin oxides after the oxides are subjected to high voltage stresses are correlated with the number of traps generated inside of the oxides by the high-voltage stresses. The densities of the traps are calculated using the tunneling front model and analyzing the transient currents that flowed through the oxide after removal of the stress voltage pulses. It is found that the trap distributions are relatively uniform throughout the small portion of the oxide sampled by the transient currents. The trap densities increase as the cube root of the fluence of electrons that passes through the oxide during the stress, independent of the stress polarity. The voltage dependence of the low-level pretunneling current is dependent on the sequence in which the stress voltage polarities and the low-level current measurement polarities are applied. The portion of the low-level pre-tunneling current that is not dependent on the polarity sequence is best fitted by a voltage dependence consistent with Schottky emission. >

Correlation of stress-induced leakage current in thin oxides with trap generation inside the oxides

Gate oxide wearout for thermally grown 57-190-A SiO/sub 2/ films in a polycrystalline silicon-SiO/sub 2/-Si structure prepared on n-type and p-type wafers was studied by examining time-dependent dielectric breakdown (TDDB) under 1-mA/cm/sup 2/ constant current with positive and negative voltages at 250 degrees C. TDDB lifetimes for positive voltage stress are more than one order longer than those for negative voltage stress. TDDB lifetimes depend on oxide thickness, that is, they increase for positive voltage stress and decreases for negative voltage stress with decreasing oxide thickness. They also depend on whether the oxide films are prepared on n-type or p-type wafers. After the positive voltage TDDB stress, negative charges are predominantly produced in the oxide layer, and the electric field at the cathode in the oxide film slightly decreases. On the contrary, after the negative voltage TDDB stress, positive charges are predominantly produced at the cathode in the oxide layer and the electric field at the cathode is built up, resulting in an increase in Fowler-Nordheim tunnel current flowing though the oxide film. >

Stress voltage polarity dependence of thermally grown thin gate oxide wearout

A novel tungsten light-shield structure has been developed. Tungsten film properties, the device configuration with the tungsten light-shield structure, and experimentally achieved results regarding device characteristics are described. Optical measurement clarified that tungsten film has a sufficiently low transmittance value for practical use for more than 200-nm-thick film and is stable up to 1000 degrees C. The good step coverage and low reflectance, such as 20-40% for aluminum, required for light-shield film were also obtained. A tungsten light-shield structure was applied to a 1/2-in format 668(H)-pixel*575(V)-pixel charge coupled-device (CCD) image sensor. An extremely low smear value, less than 0.001%, was obtained for a 300-nm film thickness. >

A novel tungsten light-shield structure for high-density CCD image sensors

A 5V Only 16Mbit Flash EEPROM Cell Using Highly Reliable Write/Erase Technologies

A 0.4- mu m stacked gate cell for a 64-Mb flash memory has been developed which has the symmetrical side wall diffusion self-aligned (SSW-DSA) structure. Using the proposed SSW-DSA cell with p/sup +/ pockets at both the drain and the source, an adequate punchthrough resistance to scale the gate length down to sub-half-micron has been obtained. It is also demonstrated that the uniform erasing scheme applying negative bias to the gate which is adopted for the SSW-DSA cell shows lower trapped charges after write/erase (W/E) cycles evaluated by a charge pumping technique, and results in better endurance and retention characteristics than nonuniform erasing schemes. This cell will enable the realization of a 64-Mb flash memory with single 5-V supply operation, 10/sup 6/ W/E endurance, and sector erasing scheme. >

A symmetrical side wall (SSW)-DSA cell for a 64 Mbit flash memory

A new silicon on insulator (SOI) wafer with epitaxial-Si/ epitaxial-MgO.Al 2 O 3 (0.1 µm)/SiO 2 (0.5 µm)/

Y. Hokari

Papers

Stress voltage polarity dependence of thermally grown thin gate oxide wearout

A novel tungsten light-shield structure for high-density CCD image sensors

A 5V Only 16Mbit Flash EEPROM Cell Using Highly Reliable Write/Erase Technologies

A symmetrical side wall (SSW)-DSA cell for a 64 Mbit flash memory

Characteristics of MOSFET prepared on Si/MgO.Al 2 O 3 /SiO 2 /Si structure