High-k gate dielectrics, particularly Hf-based materials, are likely to be implemented in CMOS advanced technologies. One of the important challenges in integrating these materials is to achieve lifetimes equal or better than their SiO/sub 2/ counterparts. In this paper we review the status of reliability studies of high-k gate dielectrics and try to illustrate it with experimental results. High-k materials show novel reliability phenomena related to the asymmetric gate band structure and the presence of fast and reversible charge. Reliability of high-k structures is influenced both by the interfacial layer as well as the high-k layer. One of the main issues is to understand these new mechanisms in order to asses the lifetime accurately and reduce them.

Review on high-k dielectrics reliability issues

Positive bias constant voltage stress combined with charge pumping (CP) measurements were applied to study trap generation phenomena in SiO 2/HfO2/TiN stacks. Using gate stacks with varying thicknesses of the interfacial SiO2 layer (IL) or high-kappa layer and analysis for frequency-dependent CP data developed to address trap depth profiling, the authors have determined that the defect generation in the stress voltage range of practical importance occurs primarily within the IL on as-grown "precursor" defects most likely caused by the overlaying HfO2 layer. The generated traps can be passivated by a forming gas or nitrogen (N2 ) anneal, whereas a postanneal stress reactivates these defects. The results obtained identify the IL as one of the major targets for reliability improvement of high-kappa stacks

Electron trap generation in high-/spl kappa/ gate stacks by constant voltage stress

Charge-pumping (CP) technique is proposed to simultaneously measure the border traps and interface-trap density (Dit). The charge pumped per cycle (Qcp) versus high level (Vh ) of gate pulse for various frequencies was used to observe the behavior of the bulk traps close to the interface as a function of the CP frequency. Evolution on Qcp as a function of frequency was successfully used to determine the depth profile of border-trap density near the high-kappa gate dielectric/Si interface. The influence of border trap in high-kappa dielectric on the Dit measurement can be prevented by an appropriate selection of gate frequency in CP technique

Depth Profiling of Border Traps in MOSFET With High- $kappa$ Gate Dielectric by Charge-Pumping Technique

Positive constant voltage stress combined with charge pumping (CP) measurements was applied to study trap generation phenomena in SiO2</sub/HfO2/TiN stacks. Using the analysis for frequency-dependent CP data developed to address depth profiling of the electron traps, we have determined that the voltage stress-induced generation of the defects contributing to threshold voltage instability in high-κ gate stacks occurs primarily within the interfacial SiO2 layer (IL) on the as-grown "precursor" defects most likely caused by the overlaying HfO2 layer. These results point to the IL as a major focus for reliability improvement of high-? stacks.

Detection of Electron Trap Generation due to Constant Voltage Stress on High-κ Gate Stacks

Electrical characterization and analysis techniques for the high-κ era

For the first time, trap density at SiO/sub 2//Si interface, HfO/sub 2//SiO/sub 2/ interface, and HfO/sub 2/ bulk of stacked HfO/sub 2//SiO/sub 2/ dielectrics are quantified respectively with a simple charge pumping method. It was found that the amount of each individual type of traps can be well correlated to specific process conditions as well as device performance, which makes such innovative characterization method very powerful for process optimization of high-k dielectrics.

Y. Jin

Papers

Direct determination of interface and bulk traps in stacked HfO/sub 2/ dielectrics using charge pumping method