Showing papers by "Yao-Wen Chang published in 1999"

Noise-constrained performance optimization by simultaneous gate and wire sizing based on Lagrangian relaxation

Abstract: Noise, as well as area, delay, and power, is one of the most important concerns in the design of deep sub-micron ICs. Currently existing algorithms can not handle simultaneous switching conditions of signals for noise minimization. In this paper, we model not only physical coupling capacitance, bur also simultaneous switching behavior for noise optimization. Based on Lagrangian relaxation, we present an algorithm that can optimally solve the simultaneous noise, area, delay, and power optimization problem by sizing circuit components. Our algorithm, with linear memory requirement overall and linear runtime per iteration, is very effective and efficient. For example, for a circuit of 6144 wires and 3512 gates, our algorithm solves the simultaneous optimization problem using only 2.1 MB memory and 47 minute runtime to achieve the precision of within 1% error on a SUN UltraSPARC-I workstation.

Universal switch blocks for three-dimensional FPGA design

Abstract: The authors consider the switch-block design problem for three-dimensional FPGAs. A three-dimensional switch block M with W terminals on each face is said to be universal if every set of nets satisfying the dimension constraint (i.e. the number of nets on each face of M is at most W) is simultaneously routable through M. A class of universal switch blocks for three-dimensional FPGAs is presented. Each of the switch blocks has 15W switches and switch-block flexibility 5 (i.e. FS =5) .I t is proved that no switch block with less than 15W switches can be universal. The proposed switch blocks are compared with others of the topology associated with those used in the Xilinx XC4000 FPGAs. Experimental results demonstrate that the proposed universal switch blocks improve routabilty at the chip level. Further, the decomposition property of a universal switch block provides a key insight into its layout implementation with a smaller silicon area. that no switch block with less than 15W switches can be universal. We also compare the proposed switch blocks with others of the topology associated with those used in the Xilinx XC4000 FPGAs. Experimental results demonstrate that the universal switch blocks improve routabilty at the chip level. 2 Switch-block modelling This Section presents the modelling for 3-D switch blocks and their routing. It is shown that the 3-D switch-block design problem can be transformed into the six-sided one. A three-dimensional switch block is a cubic block with W terminals on each face of the block. The size of the 3-D switch block is referred W. Some pairs of terminals, on different faces of the block, may have programmable switches and thus can be connected by programming the switches to be 'ON'. We represent a 3-D switch block by M3d(T, S ),w hereT is the set of terminals, and S the set of switches. Let the faces F1, F2, F3, F4, F5 ,a ndF6 represent the front, rear, left, right, top, and bottom faces, respec-

A clustering- and probability-based approach for time-multiplexed FPGA partitioning

Abstract: Improving logic density by time-sharing, time-multiplexed FPGAs (TMFPGAs) have become an important research topic for reconfigurable computing. Due to the precedence and capacity constraints in TMFPGAs, the clustering and partitioning problems for TMFPGAs are different from the traditional ones. In this paper, we propose a two-phase hierarchical approach to solve the partitioning problem for TMFPGAs. With the precedence and capacity considerations for both phases, the first phase clusters nodes to reduce the problem size, and the second phase applies a probability-based iterative-improvement approach to minimize cut cost. Experimental results based on the Xilinx TMFPGA architecture show that our algorithm significantly outperforms previous works.

Generic universal switch blocks

Abstract: A switch block M with W terminals on each side is said to be universal if every set of nets satisfying the dimension constraint (i.e., the number of nets on each side of M is at most W) is simultaneously routable through M (Y.W. Chang et al., 1996). We present an algorithm to construct N-sided universal switch blocks with W terminals on each side. Each of our universal switch blocks has (/sub 2//sup N/)W switches and switch-block flexibility N-1 (i.e., F/sub S/=N-1). We prove that no switch block with less than (/sub 2//sup N/)W switches can be universal. Further, the decomposition property of a universal switch block provides a key insight into its layout implementation with a smaller silicon area. We also compare our universal switch blocks with others of the topology associated with Xilinx XC4000-type FPGAs. Experimental results demonstrate that our universal switch blocks improve routability at the chip level.

Quasi-universal switch matrices for FPD design

Abstract: An FPD switch module M with /spl omega/ terminals on each side is said to be universal if every set of nets satisfying the dimension constraint (i.e., the number of nets on each side of EA is at most /spl omega/) is simultaneously routable through M. Chang et al. (1996) have identified a class of universal switch blocks. In this paper, we consider the design and routing problems for another popular model of switch modules called switch matrices. Unlike switch blocks, we prove that there exist no universal switch matrices. Nevertheless, we present quasi-universal switch matrices which have the maximum possible routing capacities among all switch matrices of the same size and show that their routing capacities converge to those of universal switch blocks. Each of the quasi-universal switch matrices of size /spl omega/ has a total of only 14/spl omega/-20 (14/spl omega/-21) switches if /spl omega/ is even (odd), /spl omega/>1, compared to a fully populated one which has 3/spl omega//sup 2/-2/spl omega/ switches. We prove that no switch matrix with less than 14/spl omega/-20 (14/spl omega/-21) switches can be quasi-universal. Experimental results demonstrate that the quasi-universal switch matrices improve routability at the chip level.

Programmable Logic Arrays

Abstract: The sections in this article are 1 Programming Technologies 2 Logic-Module Architecture 3 Routing Architecture 4 Commercial Cpld/Fpga Examples 5 Design Process for Programmable Logic 6 Research in Cpld/Fpga Architectures