The Fifth Edition of this academically rigorous text provides a comprehensive treatment of analog integrated circuit analysis and design starting from the basics and through current industrial practices. The authors combine bipolar, CMOS and BiCMOS analog integrated-circuit design into a unified treatment that stresses their commonalities and highlights their differences. The comprehensive coverage of the material will provide the student with valuable insights into the relative strengths and weaknesses of these important technologies.

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Analysis and Design of Analog Integrated Circuits

A digital-domain self-calibration technique, which can directly measure and cancel code errors in multistep conversions, is developed to improve the linearity of multi-step analog-to-digital converters (ADCs). While conventional self-calibration techniques require separate digital-to-analog converters (DACs) for calibration purpose to subtract nonlinearity errors in the analog domain, the proposed digital calibration technique uses add-on digital logic to subtract nonlinearity errors digitally from uncalibrated digital outputs. In a prototype 12-b fully differential two-step ADC implemented using a 2- mu m n-well CMOS technology, this technique cancels MOS switch feedthrough, op-amp offsets, and interstage gain errors simultaneously, and improves total harmonic distortion from -64 to -77 dB. >

Digital-domain calibration of multistep analog-to-digital converters

This paper presents the design of three- and nine-stage voltage-controlled ring oscillators that were fabricated in TSMC 0.18-/spl mu/m CMOS technology with oscillation frequencies up to 5.9 GHz. The circuits use a multiple-pass loop architecture and delay stages with cross-coupled FETs to aid in the switching speed and to improve the noise parameters. Measurements show that the oscillators have linear frequency-voltage characteristics over a wide tuning range, with the three- and nine-stage rings resulting in frequency ranges of 5.16-5.93 GHz and 1.1-1.86 GHz, respectively. The measured phase noise of the nine-stage ring oscillator was -105.5 dBc/Hz at a 1-MHz offset from a 1.81-GHz center frequency, whereas the value for the three-stage ring oscillator was simulated to be -99.5 dBc/Hz at a 1-MHz offset from a 5.79-GHz center frequency.

A 5.9-GHz voltage-controlled ring oscillator in 0.18-/spl mu/m CMOS

A 5.9-GHz Voltage-Controlled Ring Oscillator in 0.18- m CMOS

This paper describes a 16-bit 250 MS/s ADC fabricated on a 0.18 BiCMOS process. The ADC has an integrated input buffer with a new linearization technique that improves its distortion by 5-10 dB and lowers its power consumption by 70% relative to the state of the art. It demonstrates a new background calibration technique to correct the residue amplifier (RA) gain errors and lower its power consumption. This summing node sampling (SNS) calibration technique is based on sampling the summing-node voltage of the residue amplifier and using it with the corresponding residue to estimate the amplifier open loop gain. The ADC achieves an SNDR of 76.5 dB and consumes 850 mW from a 1.8 V supply, while the input buffer consumes 150 mW from a 3 V supply. Up to 125 MS/s, the SFDR is greater than 100 dB for input frequencies up to 100 MHz and 90 dB up to 300 MHz input frequency. At 250 MS/s, the SFDR is greater than 95 dB up to 100MHz and 85 dB up to 300 MHz.

A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration

A quantizer-subtractor circuit is provided with an input circuit (25) for inputting an input signal and a circuit (57, 59, 61 and 63) for producing a digital signal corresponding to the input signal. The quantizer-subtractor circuit contains 2" transistors (Q1 - Q4). These transistors (Q1 - Q4) are supplied with different bias voltages by a bias circuit (47). A control circuit (31, 33, 49, 35, 51, 37, 53) is connected to the transistors (Q1 - Q4) and the input circuit (25) and controls the currents passing through the 2" transistors (Q1 - Q4). A circuit (R1, R2, N1 and N2) produces as a subtraction output a signal corresponding to the difference between the controlled currents passing through the transistors (Q1, Q2) applied with the bias voltages with the odd-ordered magnitudes and the currents flowing through the transistors (Q2, Q4) applied with the bias voltages with the even-ordered magnitudes.

Quantizer-subtractor circuit

This paper demonstrates a circuit technique to improve the phase noise of a GHz-range CMOS differential LC VCO. The VCO has two on- chip transformers; primary of each transformer is used as an inductor of the LC tank. A signal current, whose frequency is the same and phase is 90 degrees in advance of the primary coil, is produced in the secondary coil so that the series resistance of the primary coil is cancelled out. As a result, Q-value of the LC tank is increased and the phase noise of a VCO is reduced. The measured phase noise of the 2.5 GHz VCO with a 100 KHz offset was -103 dBc/Hz, and the phase noise improvement in comparison with the conventional VCO at a 100 KHz frequency offset was 10 dB from a 2 V power supply.

A 2.5 GHz CMOS LC VCO with improved phase noise based on the transformer feedback scheme

This paper describes the design of a 2.7 V operational, 200 MS/s, 14-bit CMOS D/A converter (DAC). The DAC consists of 63 current cells in matrix form for an upper 6-bit sub-DAC, and 8 current cells and R-2R ladder resistors for a lower 8-bit sub-DAC. A source degeneration resistor, for which a transistor in the triode operational region is used, is connected to the source of a MOS current source transistor in a current cell in order to reduce the influence of threshold voltage (Vth) variation and to satisfy the differential nonlinearity error specification as a 14-bit DAC. In conventional high-speed and high-resolution DACs that have the same design specifications described here, spurious-free dynamic range (SFDR) characteristics commonly deteriorate drastically as the frequency of the reconstructed waveform increases. The causes of this deterioration were carefully examined in the present study, finding that the deterioration is caused in part by the input-data-dependent time-constant change at the output terminal. Unexpected current flow in parasitic capacitors associated with current sources causes the change in the output current depending on the input data, resulting in time-constant change. In order to solve this problem, we propose a new output circuit to fix the voltage at the node where the outputs of the current sources are combined. SPICE circuit simulation demonstrates that 63 dB of SFDR characteristics for the 90 MHz reconstructed waveform at the output can be realizable when the supply voltage is 2.7 V, the clock rate is 200 MS/s, and the power dissipation is estimated to be 300 mW. key words: High-speed DAC, Low-voltage DAC, High-resolution DAC, CMOS DAC, SFDR characteristics

The Design of a 2.7 V, 200 MS/s, and 14-Bit CMOS D/A Converter with 63 dB of SFDR CHaracteristics for the 90 MHz Output Signal

A new single power supply 10bit video Bi-CMOS sample-and-hold IC is described. High speed, low power and high-accuracy sample-and-hold operation has been achieved using the complementary connected buffer type sample switch. The equivalent PNP transistor is formed by the combination of NPN and PMOS transistors. The sample-and-hold IC has been implemented in 1.2um Bi-CMOS technology. The acquisition time and the switching settling time are 20ns and 15ns, respectively. It works with +5V single power supply and the power dissipation is 150mW.

http://ieeexplore.ieee.org/iel5/5468015/5468016/05468175.pdf

A Single Power Supply 10Bit Video Bi-CMOS Sample-and-Hold IC

SUMMARY We propose a fast and precise transient response and frequency characteristics simulation method for switching converters. This method uses a behavioral simulation tool without using a SPICE-like analog simulator. The nonlinear operation of the circuit is considered, and the nonlinear function is realized by defining the nonlinear formula based on the circuit operation and by applying feedback. To assess the accuracy and simulation time of the proposed simulation method, we designed currentmode buck and boost converters and fabricated them using a 0.18-μm highvoltage CMOS process. The comparison in the transient response and frequency characteristics among SPICE, the proposed program on a behavioral simulation tool which we named NSTVR (New Simulation Tool for Voltage Regulators) and experiments of fabricated IC chips showed good agreement, while NSTVR was more than 22 times faster in transient response and 85 times faster in frequency characteristics than SPICE in CPU

PAPER Special Section on Analog Circuits and Related SoC Integration Technologies A Precision and High-Speed Behavioral Simulation Method for Transient Response and Frequency Characteristics of Switching Converters

Yasuhiro Sugimoto

Papers

Quantizer-subtractor circuit

A 2.5 GHz CMOS LC VCO with improved phase noise based on the transformer feedback scheme

The Design of a 2.7 V, 200 MS/s, and 14-Bit CMOS D/A Converter with 63 dB of SFDR CHaracteristics for the 90 MHz Output Signal

A Single Power Supply 10Bit Video Bi-CMOS Sample-and-Hold IC

PAPER Special Section on Analog Circuits and Related SoC Integration Technologies A Precision and High-Speed Behavioral Simulation Method for Transient Response and Frequency Characteristics of Switching Converters