The Fifth Edition of this academically rigorous text provides a comprehensive treatment of analog integrated circuit analysis and design starting from the basics and through current industrial practices. The authors combine bipolar, CMOS and BiCMOS analog integrated-circuit design into a unified treatment that stresses their commonalities and highlights their differences. The comprehensive coverage of the material will provide the student with valuable insights into the relative strengths and weaknesses of these important technologies.

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Analysis and Design of Analog Integrated Circuits

A digital-domain self-calibration technique, which can directly measure and cancel code errors in multistep conversions, is developed to improve the linearity of multi-step analog-to-digital converters (ADCs). While conventional self-calibration techniques require separate digital-to-analog converters (DACs) for calibration purpose to subtract nonlinearity errors in the analog domain, the proposed digital calibration technique uses add-on digital logic to subtract nonlinearity errors digitally from uncalibrated digital outputs. In a prototype 12-b fully differential two-step ADC implemented using a 2- mu m n-well CMOS technology, this technique cancels MOS switch feedthrough, op-amp offsets, and interstage gain errors simultaneously, and improves total harmonic distortion from -64 to -77 dB. >

Digital-domain calibration of multistep analog-to-digital converters

This paper presents the design of three- and nine-stage voltage-controlled ring oscillators that were fabricated in TSMC 0.18-/spl mu/m CMOS technology with oscillation frequencies up to 5.9 GHz. The circuits use a multiple-pass loop architecture and delay stages with cross-coupled FETs to aid in the switching speed and to improve the noise parameters. Measurements show that the oscillators have linear frequency-voltage characteristics over a wide tuning range, with the three- and nine-stage rings resulting in frequency ranges of 5.16-5.93 GHz and 1.1-1.86 GHz, respectively. The measured phase noise of the nine-stage ring oscillator was -105.5 dBc/Hz at a 1-MHz offset from a 1.81-GHz center frequency, whereas the value for the three-stage ring oscillator was simulated to be -99.5 dBc/Hz at a 1-MHz offset from a 5.79-GHz center frequency.

A 5.9-GHz voltage-controlled ring oscillator in 0.18-/spl mu/m CMOS

A 5.9-GHz Voltage-Controlled Ring Oscillator in 0.18- m CMOS

This paper describes a 16-bit 250 MS/s ADC fabricated on a 0.18 BiCMOS process. The ADC has an integrated input buffer with a new linearization technique that improves its distortion by 5-10 dB and lowers its power consumption by 70% relative to the state of the art. It demonstrates a new background calibration technique to correct the residue amplifier (RA) gain errors and lower its power consumption. This summing node sampling (SNS) calibration technique is based on sampling the summing-node voltage of the residue amplifier and using it with the corresponding residue to estimate the amplifier open loop gain. The ADC achieves an SNDR of 76.5 dB and consumes 850 mW from a 1.8 V supply, while the input buffer consumes 150 mW from a 3 V supply. Up to 125 MS/s, the SFDR is greater than 100 dB for input frequencies up to 100 MHz and 90 dB up to 300 MHz input frequency. At 250 MS/s, the SFDR is greater than 95 dB up to 100MHz and 85 dB up to 300 MHz.

A 16-bit 250-MS/s IF Sampling Pipelined ADC With Background Calibration

A current mode sample and hold circuit has been designed to examine if high-precision current processing is possible simultaneously with a circuit to which current mode and switched-current circuits are applied and which operates at high-speed and with low supply voltage. The results are 10-bit accuracy, a 20 MHz clock, and a 2 V supply voltage. Clock feedthrough which degrades the precision of current when it is processed in a switched-current circuit is effectively canceled by the use of the newly developed differential configuration.

https://ieeexplore.ieee.org/iel3/3941/11413/00520392.pdf

A 1.6 V 10-bit 20 MHz current-mode sample and hold circuit

This invention discloses an analog/digital converter including comparator groups in which each comparator is constituted by bipolar transistors, for comparing reference voltages with an analog input voltage, and means for obtaining a digital converted value corresponding to the analog input voltage, in accordance with comparison results of in the comparator groups.

High-precision and high-speed analog/digital converter having low power consumption

A +5-V single-power-supply 10-b video BiCMOS sample-and-hold IC is described. Video speed, low power, and 10-b accuracy sample-and-hold operation have been achieved using a complementary connected buffer format sample switch. A high-speed p-n-p transistor used in the sample switch is formed by a combination of n-p-n and PMOS transistors. The sample-and-hold operation is accomplished by feeding back the hold capacitor voltage to the sample switch inputs, so that the inputs transfer symmetrically for the hold capacitor voltage at any input level. The sample-and-hold IC has been implemented in 1.2- mu m BiCMOS technology and evaluated. The following results have been obtained: 185-MHz 3-dB bandwidth at 22-pF hold capacitor, 63-dB signal-to-noise ratio at 8-MHz full-scale input, 20-ns acquisition time at 1-V step input, 15-ns switch setting time, and 0.1% linearity error. Power dissipation is 150 mW. >

A single-power-supply 10-b video BiCMOS sample-and-hold IC

The 1-V operation of a passive sigma-delta modulator has been realized. The dc voltage in the signal paths in the second-order switched capacitor filter section was set at 0.2 V so that metal-oxide-semiconductor (MOS) switches in the signal paths would have enough gate-to-source voltage to turn on without using a voltage boosting scheme. The input switch was replaced by a passive resistor to avoid floating. By modifying gain coefficients in the feedback and the input paths, the bias voltage of digital-to-analog converter (DAC) can be set to 1 V and 0 V and MOS switches become easily activated. Moreover, the correlated double sampling (CDS) scheme was adopted to suppress the 1/f noise and offset voltage produced at the input of a comparator. Successful operation from 1-V supply voltage was confirmed by circuit simulation using the 0.18-um complementary MOS (CMOS) process.

Design of a 1-V operational passive sigma-delta modulator

In a disclosed amplifier circuit, P channel MOS transistors, as input elements, are connected at the sources to the emitters of bipolar transistors.

Yasuhiro Sugimoto

Papers

A 1.6 V 10-bit 20 MHz current-mode sample and hold circuit

High-precision and high-speed analog/digital converter having low power consumption

A single-power-supply 10-b video BiCMOS sample-and-hold IC

Design of a 1-V operational passive sigma-delta modulator

Amplifier circuit using a P channel MOS transistor