In this article a review of low temperature (LT) (≤500 °C) process modules in view of 3-D sequential integration is presented. First, both the bottom device thermal stability and intermediate back end of line (iBEOL) versus thermal anneal and ns-laser anneal is determined, setting up the top device temperature fabrication process at 500 °C during a couple of hours. Then, the full LT process flow with process modules developed at 500 °C is exposed. Great progress and breakthrough for high performance (HP) digital stacked FETs has been made recently. Areas previously considered as potential showstoppers have been overcome: 1) efficient contamination containment for wafers with Cu/ultra low- ${k}$ (ULK) iBEOL enabling their reintroduction in front end of line (FEOL) for top FET processing; 2) low-resistance poly-Si gate for the top FETs and solutions for improving gate-stack reliability; and 3) full LT raised source drain (RSD) epitaxy including surface preparation combined with SiCO 400 °C spacer and SPER junctions activation. Finally, the first functional nMOS and pMOS demonstration with a 500 °C thermal budget (TB) is highlighted.

A Review of Low Temperature Process Modules Leading Up to the First (≤500 °C) Planar FDSOI CMOS Devices for 3-D Sequential Integration

Ultrathin-body (UTB) (111) InAs-On-Insulator (InAs-OI) n-channel metal–oxide–semiconductor field-effect transistors (nMOSFETs) are proposed as a new technology booster using the L valley conduction in III–V channels. The performance of the conventional UTB III–V nMOSFETs is limited by the essential band features of the $\Gamma $ valley conduction such as the low density of states, resulting in low inversion capacitance, and the light effective mass ${m}_{z}$ along the confinement direction, resulting in strong thickness fluctuation scattering. The strong confinement of electrons by a combination of (111) surface orientation and UTB InAs-OI structures is expected to transfer the electrons into the L valley with much heavier ${m}_{z}$ than in the $\Gamma $ valley, leading to higher semiconductor capacitance and suppression of thickness fluctuation scattering. We also experimentally demonstrate the UTB (111) InAs-OI nMOSFETs operation with thinning the InAs channels down to 3 nm, realized by the smart-cut and digital etching process. Channel thickness scaling improves both the OFF- and ON-currents by expansion of the effective bandgap. It is shown that the measured mobility increases with decreasing InAs-OI thickness from 4.8 to 4.4 nm, which is attributable to the increase in the electron occupancy in the L valley.

Proposal and Experimental Demonstration of Ultrathin-Body (111) InAs-On-Insulator nMOSFETs With L Valley Conduction

We demonstrated low temperature ( 2 O 5 -RRAM and a-IGZO photo detector devices on the upper transferred Si layer were vertically stacked with CMOS circuits. Bonding and top Si layer transfer are considerably affected by ion implantation process, ILD, surface treatment, oxide CMP and annealing. Different light intensity to photodetector at the upper layer modulates the frequency of current sensor with 21 stage ring- oscillator at the lower layer and current level in RRAM at the upper layer is also modulated by input frequency from CMOS devices. The functionalities of ion-cut based M3D integration platform are confirmed by higher frequency and current level with respect to light intensity.

Low Temperature and Ion-Cut Based Monolithic 3D Process Integration Platform Incorporated with CMOS, RRAM and Photo-Sensor Circuits

A single-crystal islands (SCI) technique using low thermal budget pulse laser process is proposed and demonstrated to fabricate single-crystal silicon islands over amorphous dielectric for monolithic 3-D and back-end-of-line (BEOL) FinFET circuits. By laser recrystallizing mask-defined a-Si islands encapsulated with conformal silicon nitride film, designed single-crystal Si islands can be obtained. The single crystallinity of the island are verified with SECCO Etch, high-resolution electron microscopy (HREM), transmission electron microscopy (TEM), and electron backside scattering (EBSD). About 40 nm FinFETs were successfully fabricated in the SCI Si islands and shown to exhibit excellent electrical performance and low variability that are compatible with the FinFETs fabricated on commercial silicon-on-insulator (SOI) wafer.

Single-Crystal Islands (SCI) for Monolithic 3-D and Back-End-of-Line FinFET Circuits

A 3D micro display, the micro display including: a first single crystal layer including at least one LED driving circuit; and a second single crystal layer including a plurality of light emitting diodes (LEDs), where the second single crystal layer overlays the first single crystal layer, where the second single crystal layer includes at least ten first LED pixels, and where the second single crystal layer and the first single crystal layer are separated by a vertical distance of less than ten microns.

3D microdisplay device and structure

Monolithic 3D back-end of line (BEOL) FinFET switch arrays are demonstrated in large single crystalline Si islands (2.56 μm2), whose location, size and shape are determined by design. Details of the improved location-controlled-grain (LCG) technique are presented. A voltage regulator implemented with the BEOL switch arrays using external control signals shows better theoretical figure of merit (FOM) of 0.089ns than 2D voltage regulators of 0.43ns.

Yi-Jui Chang

Papers

Monolithic 3D BEOL FinFET switch arrays using location-controlled-grain technique in voltage regulator with better FOM than 2D regulators