An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

In this paper, recent progress of phase change memory (PCM) is reviewed. The electrical and thermal properties of phase change materials are surveyed with a focus on the scalability of the materials and their impact on device design. Innovations in the device structure, memory cell selector, and strategies for achieving multibit operation and 3-D, multilayer high-density memory arrays are described. The scaling properties of PCM are illustrated with recent experimental results using special device test structures and novel material synthesis. Factors affecting the reliability of PCM are discussed.

Phase Change Memory

Six years after their birth, terahertz quantum-cascade lasers can now deliver milliwatts or more of continuous-wave coherent radiation throughout the terahertz range — the spectral regime between millimetre and infrared wavelengths, which has long resisted development. This paper reviews the state-of-the-art and future prospects for these lasers, including efforts to increase their operating temperatures, deliver higher output powers and emit longer wavelengths.

Terahertz quantum-cascade lasers

A phase-change memory element with side-wall contacts is disclosed, which has a bottom electrode. A non-metallic layer is formed on the electrode, exposing the periphery of the top surface of the electrode. A first electrical contact is on the non-metallic layer to connect the electrode. A dielectric layer is on and covering the first electrical contact. A second electrical contact is on the dielectric layer. An opening is to pass through the second electrical contact, the dielectric layer, and the first electrical contact and preferably separated from the electrode by the non-metallic layer. A phase-change material is to occupy one portion of the opening, wherein the first and second electrical contacts interface the phase-change material at the side-walls of the phase-change material. A second non-metallic layer may be formed on the second electrical contact. A top electrode contacts the top surface of the outstanding terminal of the second electrical contact.

Phase-change memory

The authors survey the current state of phase change memory (PCM), a nonvolatile solid-state memory technology built around the large electrical contrast between the highly resistive amorphous and highly conductive crystalline states in so-called phase change materials. PCM technology has made rapid progress in a short time, having passed older technologies in terms of both sophisticated demonstrations of scaling to small device dimensions, as well as integrated large-array demonstrators with impressive retention, endurance, performance, and yield characteristics. They introduce the physics behind PCM technology, assess how its characteristics match up with various potential applications across the memory-storage hierarchy, and discuss its strengths including scalability and rapid switching speed. Challenges for the technology are addressed, including the design of PCM cells for low reset current, the need to control device-to-device variability, and undesirable changes in the phase change material that c...

Phase change memory technology

Wafer-level bonding/stacking technology for 3D integration

An overview of wafer-level three-dimensional (3D)) integration technology is provided. The basic reasoning for pursuing 3D integration is presented, followed by a description of the possible process variations and integration schemes, as well as the process technology elements needed to implement 3D integrated circuits. Detailed descriptions of two wafer-level integration schemes implemented at IBM are given, and the challenges of bringing 3D integration into a production environment are discussed.

Wafer-level 3D integration technology

We present an overview of a new monolithic fabrication technology known as three-dimensional integration. 3D integration refers to any process by which multiple conventional device layers may be stacked and electrically interconnected. By combining state-of-the-art single-wafer integration with a high-density inter-wafer interconnect, our 3D integration process is capable of providing improved circuit performance in terms of metrics such as wire length, area, timing, and energy consumption. In this paper, we will discuss the overall 3D integration process flow, as well as specific technological challenges and the issues they present to circuit designers. We will also describe how these issues may be tackled during the placement, routing, and layout stages of physical design. Finally, we will present some performance results that may be obtained by integrating circuits in three dimensions.

Technology, performance, and computer-aided design of three-dimensional integrated circuits

The morphology and bond strength of copper-bonded wafer pairs prepared under different bonding/annealing temperatures and durations are presented. The interfacial morphology was examined by transmission electron microscopy while the bond strength was examined from a diesaw test. Physical mechanisms explaining the different roles of postbonding anneals at temperatures above and below 300°C are discussed. A map summarizing these results provides a useful reference on process conditions suitable for actual microelectronics fabrication and three-dimensional integrated circuits based on Cu wafer bonding. © 2003 The Electrochemical Society. All rights reserved.

https://iopscience.iop.org/article/10.1149/1.1626994/pdf

Morphology and Bond Strength of Copper Wafer Bonding

https://ir.nctu.edu.tw:443/bitstream/11536/15218/1/000300190600002.pdf

Kuan-Neng Chen

Papers

Wafer-level bonding/stacking technology for 3D integration

Wafer-level 3D integration technology

Technology, performance, and computer-aided design of three-dimensional integrated circuits

Morphology and Bond Strength of Copper Wafer Bonding

Low temperature bonding technology for 3D integration