Flexible and stretchable electronics can dramatically enhance the application of electronics for the emerging Internet of Everything applications where people, processes, data and devices will be integrated and connected, to augment quality of life. Using naturally flexible and stretchable polymeric substrates in combination with emerging organic and molecular materials, nanowires, nanoribbons, nanotubes, and 2D atomic crystal structured materials, significant progress has been made in the general area of such electronics. However, high volume manufacturing, reliability and performance per cost remain elusive goals for wide commercialization of these electronics. On the other hand, highly sophisticated but extremely reliable, batch-fabrication-capable and mature complementary metal oxide semiconductor (CMOS)-based technology has facilitated tremendous growth of today's digital world using thin-film-based electronics; in particular, bulk monocrystalline silicon (100) which is used in most of the electronics existing today. However, one fundamental challenge is that state-of-the-art CMOS electronics are physically rigid and brittle. Therefore, in this work, how CMOS-technology-enabled flexible and stretchable electronics can be developed is discussed, with particular focus on bulk monocrystalline silicon (100). A comprehensive information base to realistically devise an integration strategy by rational design of materials, devices and processes for Internet of Everything electronics is offered.

CMOS-Technology-Enabled Flexible and Stretchable Electronics for Internet of Everything Applications.

After two decades of intensive development, 3-D integration has proven invaluable for allowing integrated circuits to adhere to Moore’s Law without needing to continuously shrink feature sizes The 3-D integration is also an enabling technology for hetero-integration of microelectromechanical systems (MEMS)/microsensors with different technologies, such as CMOS and optoelectronics This 3-D hetero-integration allows for the development of highly integrated multifunctional microsystems with small footprints, low cost, and high performance demanded by emerging applications This paper reviews the following aspects of the MEMS/microsensor-centered 3-D integration: fabrication technologies and processes, processing considerations and strategies for 3-D integration, integrated device configurations and wafer-level packaging, and applications and commercial MEMS/microsensor products using 3-D integration technologies Of particular interest throughout this paper is the hetero-integration of the MEMS and CMOS technologies [2015-0158]

3-D Integration and Through-Silicon Vias in MEMS and Microsensors

This paper reports the wireless control of bulk-micromachined shape-memory-alloy actuators using external radiofrequency magnetic fields and its application to microgrippers. The frequency-sensitive wireless resonant heater to which the gripper actuator is bonded is activated only when the field frequency is tuned to the resonant frequency of the heater. A batch-compatible bonding technique based on photo-defined copper electroplating is developed to mechanically and thermally couple the gripper with the planar heater circuit fabricated using copper-clad polyimide film. The actuation range of 600 μm as the tip opening distance is obtained with normally closed 5-mm long grippers at a device temperature of 92 °C. The field frequency range to which the devices with 140-MHz resonant frequency respond is measured to be ∼13 MHz about the resonant frequency. The manipulation of vertically aligned carbon-nanotube forests is experimentally demonstrated. Mechanical stress tests for the bond formed by the developed electroplating bonding method show a shear strength greater than 40 MPa.

Frequency-controlled wireless shape-memory-alloy microactuators integrated using an electroplating bonding process

In this paper a wafer-level process is proposed to fully integrate carbon-based micro-supercapacitor onto silicon substrate. This process relies on the deposition of a paste containing carbon, PVDF and acetone into cavities etched in silicon. After electrolyte deposition in a controlled atmosphere, a wafer-level encapsulation is realized. Cyclic voltammetry performed on non-encapsulated micro-components showed specific energy of 257 mJ cm−2 for 336 μm deep cavities. The specific encapsulation process developed was tested separately and proved to be efficient in terms of resistance to organic electrolytes and mechanical strength.

/pdf/wafer-level-fabrication-process-for-fully-encapsulated-micro-4gyz746ytw.pdf

Wafer-level fabrication process for fully encapsulated micro-supercapacitors with high specific energy

Development of devices that can be fabricated on amorphous substrates using multiple single-crystal semiconductors with different physical, electrical, and optical characteristics is important for highly efficient portable and flexible electronics, optoelectronics, and energy conversion devices. Reducing the use of single-crystal substrates can contribute to low-cost and environmentally benign devices covering a large area. We demonstrate a technique to harvest and transfer vertically aligned single-crystal semiconductor micro- and nanopillars from a single-crystal substrate to a low-cost carrier substrate while simultaneously preserving the integrity, order, shape, and fidelity of the transferred pillar arrays. The transfer technique facilitates multilayer process integration by exploiting a vertical embossing and lateral fracturing method using a spin-coated polymer layer on a carrier substrate. Electrical contacts are formed using a bilayer of metal and conducting polymer such as gold (Au) and polyaniline (PAni). In this method, the original single-crystal substrate can be repeatedly used for generating more devices and is minimally consumed, whereas in conventional fabrication methods, the substrate is employed solely as a mechanical support. This heterogeneous integration technique potentially offers devices with low physical fill factor contributing to lower leakage current and noise, reduced parasitic capacitance, and enhanced photon-semiconductor interactions, and enables heterogeneous multimaterial integration such as silicon with compound semiconductors for rapidly expanding large-scale applications, including low-cost and flexible electronics, displays, tactile sensors, and energy conversion systems.

/pdf/harvesting-and-transferring-vertical-pillar-arrays-of-single-3v3p4ukj4f.pdf

Harvesting and Transferring Vertical Pillar Arrays of Single-Crystal Semiconductor Devices to Arbitrary Substrates

In this paper, we report on a technology for wafer-level MEMS packaging with vertical via holes and low temperature bonding using a patternable B stage epoxy. We fabricated via holes for vertical feed-throughs and then applied bottom-up copper electroplating to fill the via holes. For low temperature wafer level packaging, we used B-stage epoxy bonding in the sealing line. The optimal bonding parameters were 150 °C and 30 min. The tensile strength was about 15 MPa. Therefore, this packaging technology can be used for low temperature wafer level packaging for many MEMS devices.

Low temperature epoxy bonding for wafer level MEMS packaging

This paper describes a temperature management system for a deformable mirrors of piezo-actuated display package (PADP). This package which is integrated in microbeam projectors is used in portable devices such as cellphones, laptops, and personal digital assistants (PDAs), to name a few. Ambient temperature change is a critical factor affecting the performance of PADP. To reduce this effect of ambient temperature change, a temperature control system using a microheater and a temperature feedback circuit is developed. A computational model of the transient thermal analysis for the feedback control system is also developed. The obtained theoretical results are in a good agreement with the experimental measurements. Under this controlled system, the magnitude of the temperature fluctuation is reduced by ±0.5 °C. In order to enhance the performance of the developed system, various values of the temperature sensor resistance are used, leading to a reduction of about 10% of the temperature fluctuation.

Development of temperature feedback control system for piezo-actuated display package

In this paper, we report a new technology for lightweight, low temperature bonding process with thin film polymer microcap. Polymer (SU-8) was used both for the intermediate adhesive layer and as a cap structure. Silicon oxide thin film was deposited using furnace to separate the microcap from the carrier wafer. The measured tensile strength of the package is in the range of 7-17 MPa. This thin-film polymer microcap on the host wafer was successfully demonstrated through low-temperature bonding and bulk micromachining. The experimental result shows that relatively high bonding strength at low bonding temperature can be achieved.

A Novel Low-Temperature Microcap Packaging using SU-8 Bonding

Polymer-Metal Composite Thin Film Microcap Packaging Technology Using Low Temperature SU-8 Bonding Jinnil Choi1, Yong-Kook Kim2, Soo-Won Kim2, Byung Hyun Nam1, and Byeong-Kwon Ju3 ∗ 1Department of Mechanical Engineering, Hanbat National University, Daejeon 305-719, Republic of Korea 2Department of Electronics and Computer Engineering, Korea University, Seoul 136-713, Republic of Korea 3Display and Nanosystem Laboratory, College of Engineering, Korea University, Seoul 136-713, Republic of Korea

Polymer-metal composite thin film microcap packaging technology using low temperature SU-8 bonding

In this paper we report a technology for lightweight, small radio-frequency (rf) microelectromechanical system packaging with a short electrical path length. We used an ultrathin silicon substrate as the packaging substrate. Via holes for vertical feed-through were fabricated on the thin silicon wafer. Then, bottom-up gold electroplating was applied to fill via holes. For hermetic sealing, gold-gold direct metal bonding was used in the sealing line. The packaged rf device has a reflection loss below -22 dB and an insertion loss of -0.05 to -0.08 dB. Therefore, with the ultrathin silicon wafer, a lightweight, small device package can be constructed.

Yong Kook Kim

Papers

Low temperature epoxy bonding for wafer level MEMS packaging

Development of temperature feedback control system for piezo-actuated display package

A Novel Low-Temperature Microcap Packaging using SU-8 Bonding

Polymer-metal composite thin film microcap packaging technology using low temperature SU-8 bonding

Ultrathin silicon micropackaging for RF MEMS devices