Method and system for simulating state retention of an RTL design are disclosed. The method includes receiving a netlist description of the circuit represented in a register-transfer-level (RTL) design environment, receiving power information specifications of the circuit, identifying one or more power domains of the circuit using the netlist description and the power information specifications, associating the one or more power domains and the power information specifications in the RTL design environment, where the one or more power domains are controlled by a set of power control signals through a power manager logic, and simulating state retention behavior in response to variations in power applied to the power domain.

Method and system for simulating state retention of an rtl design

A low power integrated circuit design verification method and tool for automatically synthesizing a set of low power assertions from statements of low power intent. The low power intent statements provide low power constraint information for an integrated circuit design. The low power assertions are automatically synthesized from the low power intent statements and may be used to monitor, check and verify power controller signals. The low power assertions may also be used to collect low power functional coverage data.

Synthesis of assertions from statements of power intent

A computer-implemented method for debugging the power aspect of an IC design by integrating the power specification expressed in certain power specification format and its corresponding circuit design within a power schematic diagram called power map. Power map is created by using a power data base generated by regrouping the original circuit design hierarchy to new hierarchies defined by the power specification. Power map contains power cell symbols (such as isolation cells, level shifters, power switches) and signal nets, and can show the relationship between power domains. Power map can also display mismatches or errors between the power specification and the circuit design for those signals connecting the power domains. Furthermore, power map can be used in conjunction with simulation result.

Hierarchical power map for low power design

Disclosed are a method, system, and computer program product for implementing various embodiments of the methods for implementing multi-power domain digital or mixed-signal verification and low power simulation. The method or the system comprises automatically generating one or more net or terminal expression, set, or one or more overriding net or terminal expression by reading, importing, or interpreting the power data file for the electronic circuit design; identifying one or more schematics of the electronic circuit design; generating an annotated schematic of the electronic circuit design by automatically annotating at least one of the one or more schematics with some of the one or more net or terminal expression, set, or one or more overriding net or terminal expression; and performing verification of the electronic circuit design by using at least the annotated schematic.

Method, system, and computer program product for implementing multi-power domain digital / mixed-signal verification and low power simulation

Certain exemplary embodiments can provide a system, machine, device, manufacture, circuit, and/or user interface adapted for, and/or a method and/or machine-readable medium comprising machine-implementable instructions for, activities that can comprise, based on a predicted non-zero future power requirement for performing one or more portions of an expected workload by a predetermined system, the predicted future power requirement based on a past power requirement for performing one or more portions of a known workload by the predetermined system, automatically causing a change from a first power state of the predetermined system to a second power state that does not violate a specification for performing the one or more portions of the expected workload.

Systems, devices, and/or methods for managing energy usage

A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.

Yonghao Chen

Papers

Method and mechanism for implementing electronic designs having power information specifications background