A pulse photometer adapted to observe a pulse wave of a living body is disclosed. A light emitter is adapted to irradiate the living body with a first light beam having a first wavelength and a second light beam having a second wavelength which is different from the first wavelength. A converter is operable to convert the first light beam and the second light beam, which have been reflected or transmitted from the living body, into a first data set corresponding to the first wavelength and a second data set corresponding to the second wavelength. A processor is operable to process the first data set and the second data set with a rotating matrix to separate a signal component and a noise component contained in the pulse wave.

Signal processing method, and pulse photometer using the method

Clock gating is a power reduction technique that has been used successfully in the custom ASIC domain. Clock and logic signal power are saved by temporarily disabling the clock signal on registers whose outputs do not affect circuit outputs. We consider and evaluate FPGA clock network architectures with built-in clock gating capability and describe a flexible placement algorithm that can operate with various gating granularities (various sizes of device regions containing clock loads that can be gated together). Results show that depending on the clock gating architecture and the fraction of time clock signals are enabled, clock power can be reduced by over 50%, and results suggest that a fine granularity gating architecture yields significant power benefits.

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Clock gating architectures for FPGA power reduction

Method and system for simulating state retention of an RTL design are disclosed. The method includes receiving a netlist description of the circuit represented in a register-transfer-level (RTL) design environment, receiving power information specifications of the circuit, identifying one or more power domains of the circuit using the netlist description and the power information specifications, associating the one or more power domains and the power information specifications in the RTL design environment, where the one or more power domains are controlled by a set of power control signals through a power manager logic, and simulating state retention behavior in response to variations in power applied to the power domain.

Method and system for simulating state retention of an rtl design

A low power integrated circuit design verification method and tool for automatically synthesizing a set of low power assertions from statements of low power intent. The low power intent statements provide low power constraint information for an integrated circuit design. The low power assertions are automatically synthesized from the low power intent statements and may be used to monitor, check and verify power controller signals. The low power assertions may also be used to collect low power functional coverage data.

Synthesis of assertions from statements of power intent

Systems, methods, and apparatuses relating to a configurable spatial accelerator are described In one embodiment, a processor includes a core with a decoder to decode an instruction into a decoded instruction and an execution unit to execute the decoded instruction to perform a first operation; a plurality of processing elements; and an interconnect network between the plurality of processing elements to receive an input of a dataflow graph comprising a plurality of nodes, wherein the dataflow graph is to be overlaid into the interconnect network and the plurality of processing elements with each node represented as a dataflow operator in the plurality of processing elements, and the plurality of processing elements are to perform a second operation by a respective, incoming operand set arriving at each of the dataflow operators of the plurality of processing elements

Processors, methods, and systems with a configurable spatial accelerator

A method of adding power control circuitry to a circuit design at each of an RTL and a netlist level comprising: demarcating multiple power domains within the circuit design; specifying multiple power modes each power mode corresponding to a different combination of on/off states of the multiple demarcated power domains; and defining isolation behavior relative to respective power domains.

Method and mechanism for implementing electronic designs having power information specifications background

A method is provided to select circuit cells for use in optimization of an integrated circuit design from among a plurality of circuit cells within a cell library, the method comprising: obtaining a value for each cell of the plurality that is indicative of both the cell's power dissipation and the cell's rate of output voltage change; ordering the cells of the plurality based upon the values; identifying a difference between values of cells that are proximate each other within the ordering of the cells that meets a threshold; and designating a cut point within the ordering of the cells based upon the identified difference.

Selection of cells from a multiple threshold voltage cell library for optimized mapping to a multi-vt circuit

A circuit design synthesis method is provided comprising: associating a first cell library with a first block of a circuit design; associating a second cell library with a second block of the circuit design; specifying at least one constraint upon the overall circuit design; mapping a portion of the first block to a cell in the first cell library based upon the at least one constraint in view of a step of mapping a portion of the second block to a cell in the second cell library; and mapping a portion of the second block to a cell in the second cell library based upon the at least one constraint in view of the step of mapping a portion of the first block to a cell in the first cell library.

Optimized mapping of an integrated circuit design to multiple cell libraries during a single synthesis pass

A method and system are provided for computing behavioral level observabilities of a digital system. In one example, a logic network is provided for performing an observability analysis at the behavioral level of a digital system. The logic network includes logic objects configured to emulate behavioral observabilities computed from a control data flow graph (CDFG), wherein the logic objects include at least one of: first logic objects configured to compute a token observable condition (TOC) of an edge of the CDFG; and second logic objects configured to compute a node observable condition (NOC) of a node of the CDFG. A logic optimization is used to optimize the logic network to obtain an optimized logic network of the behavioral observabilities.

Behavioral level observability analysis and its applications

Clock root gating transformation targets power savings on the clock tree by inserting gating logic at the root of the clock. In this paper, we propose an efficient graph-based algorithm to solve the root clock gating optimization problem. The algorithm is also tightly integrated with a clock tree synthesis tool so that real power savings can be achieved after the clock tree is generated. Experimental results on industrial circuits showed that significant power savings can be achieved.

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Qi Wang

Papers

Method and mechanism for implementing electronic designs having power information specifications background

Selection of cells from a multiple threshold voltage cell library for optimized mapping to a multi-vt circuit

Optimized mapping of an integrated circuit design to multiple cell libraries during a single synthesis pass

Behavioral level observability analysis and its applications

Power minimization by clock root gating