Showing papers by "Yoshihito Amemiya published in 2009"
TL;DR: A low-power CMOS voltage reference was developed using a 0.35 mum standard CMOS process technology and would be suitable for use in subthreshold-operated, power-aware LSIs.
Abstract: A low-power CMOS voltage reference was developed using a 0.35 mum standard CMOS process technology. The device consists of MOSFET circuits operated in the subthreshold region and uses no resistors. It generates two voltages having opposite temperature coefficients and adds them to produce an output voltage with a near-zero temperature coefficient. The resulting voltage is equal to the extrapolated threshold voltage of a MOSFET at absolute zero temperature, which was about 745 mV for the MOSFETs we used. The temperature coefficient of the voltage was 7 ppm/degC at best and 15 ppm/degC on average, in a range from - 20 to 80degC. The line sensitivity was 20 ppm/V in a supply voltage range of 1.4-3 V, and the power supply rejection ratio (PSRR) was -45 dB at 100 Hz. The power dissipation was 0.3 muW at 80degC. The chip area was 0.05 mm2 . Our device would be suitable for use in subthreshold-operated, power-aware LSIs.
346 citations
10 Nov 2009
TL;DR: A temperature- and supply-independent clock generator has been developed using 0.35-µm CMOS technology and can be implemented monolithically without using LC resonant circuits, quartz resonators, and MEMS oscillators.
Abstract: A temperature- and supply-independent clock generator has been developed using 0.35-µm CMOS technology. This generator is based on a simple frequency-locked loop technique and can be implemented monolithically without using LC resonant circuits, quartz resonators, and MEMS oscillators. A sample device that is tunable over a wide frequency range of 2–100 MHz was designed and fabricated. It showed a temperature coefficient of 90 ppm/°C, a line regulation of 4%/V, and a power dissipation of 180 µW, at a frequency of 30 MHz. The process sensitivity (σ/μ) was 2.7%. This clock generator can be used as an on-chip reference clock circuit.
44 citations
21 Jun 2009
TL;DR: In this article, an ultra-low-power temperature sensor circuit was developed using a 0.35-µm standard CMOS process, which consists of a proportional-to-absolute temperature (PTAT) current generator and a frequency-locked loop, and generates a PTAT clock frequency.
Abstract: An ultra-low-power temperature sensor circuit has been developed using a 0.35-µm standard CMOS process. The circuit consists of a proportional-to-absolute-temperature (PTAT) current generator and a frequency-locked loop, and generates a PTAT clock frequency. The PTAT current generator is the key component of the sensor and was constructed by using the characteristics of a MOSFET in the subthreshold region. Theoretical analyses and experimental results showed that the circuit can be used as a temperature sensor with ultra-low-power consumption of 10 µW or less. The accuracy of the sensor output was within ±1.8°C in a temperature range from 10°C to 80°C. Our sensor would be suitable for use in subthreshold-operated, power-aware LSIs.
20 citations
24 May 2009
TL;DR: The proposed compensation technique uses a reference current that is independent of PVT variations to mitigate the degradation of circuit performance with PVT variation in low-voltage digital circuits.
Abstract: An on-chip process, supply voltage, and temperature (PVT) compensation technique for a low-voltage CMOS digital circuit is proposed. Because the degradation of circuit performance originates from the variation of the saturation current, a compensation technique that uses a reference current that is independent of PVT variations was developed. The operations of the circuit were confirmed by SPICE simulation with a set of 0.35-µm standard CMOS parameters. Moreover, Monte Carlo simulations assuming process spread and device mismatch in all MOSFETs showed the effectiveness of the proposed technique and achieved performance improvement of 74%. The circuit is useful for on-chip compensation to mitigate the degradation of circuit performance with PVT variation in low-voltage digital circuits.
9 citations
01 Dec 2009
TL;DR: An offset cancellation technique for fully differential amplifiers is proposed, which uses subthreshold-operated operational amplifiers (subth-OP amps) for feedback biasing and results for the simulation and fabrication are described.
Abstract: An offset cancellation technique for fully differential amplifiers is proposed. This technique uses subthreshold-operated operational amplifiers (subth-OP amps) for feedback biasing. Two subth-OP amps sense the two outputs of the differential amplifier and accordingly adjust the load currents in the amplifier to fix the outputs to a given reference voltage. The feedback operation is established only at dc and low frequencies because the subth-OP amps operate very slowly. The differential amplifier consequently operates as a high-pass filter and therefore shows no dc offset in its output, while it can normally amplify ac input signals. The results for the simulation and fabrication of the device are described.
9 citations
TL;DR: The threshold-logic gate device consisting of subthreshold MOSFET circuits is proposed, which has a simple structure and operates at low power dissipation, so it is suitable for constructing cell-based, parallel processing LSIs such as cellular-automaton and neural-network LSIs.
Abstract: SUMMARY A threshold-logic gate device consisting of subthreshold MOSFET circuits is proposed. The gate device performs threshold-logic operation, using the technique of current-mode addition and subtraction. Sample digital subsystems, i.e., adders and morphological operation cells based on threshold logic, are designed using the gate devices, and their operations are confirmed by computer simulation. The device has a simple structure and operates at low power dissipation, so it is suitable for constructing cell-based, parallel processing LSIs such as cellular-automaton and neural-network LSIs.
6 citations
01 Jul 2009
TL;DR: An ultra-low power temperature sensor circuit based on a subthreshold MOSFET was proposed in this paper, which consists of a modified β-multiplier self biasing circuit that uses a switched capacitor resistor instead of ordinary resistors.
Abstract: An ultra-low power temperature sensor circuit based on a subthreshold MOSFET was proposed. The sensor consists of a modified β-multiplier self biasing circuit that uses a switched capacitor resistor instead of ordinary resistors. The circuit is operated in the subthreshold region, and it generates a proportional to absolute temperature (PTAT) voltage. Simulation with SPICE demonstrated that the circuit can be used as a smart temperature sensor with ultra-low power consumption of 3.5 ㎼ or less. The accuracy of the sensor output was within ±1.5℃.
6 citations
24 May 2009
TL;DR: A low power on-chip reference clock generator consisting of subthreshold MOSFET circuits with no inductor, quartz resonator, or MEMS oscillator that can be used as a reference clock for intermittent operation in power aware LSIs.
Abstract: A low power on-chip reference clock generator consisting of subthreshold MOSFET circuits is proposed. It uses a simple frequency-locked loop technique with no inductor, quartz resonator, or MEMS oscillator. Theoretical analyses and a SPICE simulation with 0.35-µm CMOS parameters showed that the clock frequency could be controlled in the frequency range of 10–1000 kHz. When operated at 170 kHz, the generator showed a temperature coefficient of 100 ppm/°C, a line sensitivity of 3%/V, and a power consumption of 20 µW. Our clock generator can be used as a reference clock for intermittent operation in power aware LSIs.
5 citations
TL;DR: A new class of stochastic resonance is found in a simple neural network that consists of photoreceptors generating nonuniform outputs for common inputs with random offsets and an ensemble of noisy McCulloch-Pitts neurons each of which has random threshold values in the temporal domain.
Abstract: SUMMARY We found a new class of stochastic resonance (SR) in a simple neural network that consists of i) photoreceptors generating nonuniform outputs for common inputs with random offsets, ii) an ensemble of noisy McCulloch-Pitts (MP) neurons each of which has random threshold values in the temporal domain, iii) local coupling connections between the photoreceptors and the MP neurons with variable receptive fields (RFs), iv) output cells, and v) local coupling connections between the MP neurons and the output cells. We calculated correlation values between the inputs and the outputs as a function of the RF size and intensities of the random components in photoreceptors and the MP neurons. We show the existence of “optimal noise intensities” of the MP neurons under the nonidentical photoreceptors and “nonzero optimal RF sizes,” which indicated that optimal correlation values of this SR model were determined by two critical parameters; noise intensities (well-known) and RF sizes as a new
4 citations
19 Jan 2009
TL;DR: In this paper, an ultra-low power CMOS voltage reference circuit has been fabricated in a 0.35-μm standard CMOS process, which generates a reference voltage based on threshold voltage of a MOSFET at absolute zero temperature.
Abstract: An ultra-low power CMOS voltage reference circuit has been fabricated in a 0.35-μm standard CMOS process. The circuit generates a reference voltage based on threshold voltage of a MOSFET at absolute zero temperature. Theoretical analyses and experimental results showed that the circuit generates a quite stable reference voltage of 745 mV on average. The temperature coefficient and line sensitivity of the circuit were 7 ppm/°C and 20 ppm/V, respectively. The power supply rejection ratio (PSRR) was -45 dB at 100 Hz. The circuit consists of subthreshold MOSFETs with a low-power dissipation of 0.3 μW or less and a 1.5-V power supply. Because the circuit generates a reference voltage based on threshold voltage of a MOSFET in an LSI chip, it can be used as an on-chip process monitoring circuit and as a part of the on-chip process compensation circuit systems.
3 citations
Journal Article•
TL;DR: In this article, a single-electron circuit performing edge detection was proposed, and the basic operations were demonstrated using a single image processing structure for the single-input single-output (SISO) circuit.
Abstract: Single-electron circuits can be considered as highly functional units both in digital and analog computational systems. On the other hand, electrical circuits that are designed by mimicking computational structures in living organisms - neuromorphic circuits, would provide an insight to develop even more efficient processors. Neuromorphic systems have extensively been studied only for CMOS devices, and several neuromorphic circuits have been designed and fabricated. In this work, as an example toward developing nano-electronic neuromorphic architectures, we propose a possible image-processing structure for single-electron circuits. Among early visual processing, edge detection is a primary function in the vertebrate retina. We thus propose a single-electron circuit performing edge detection, and demonstrate the basic operations.
01 Jan 2009
TL;DR: In this paper, an ultra-low power clock reference generator was developed using a 0.35-µm CMOS parameters, which is based on a simple frequency-locked loop technique with no inductors, quartz resonators, and MEMS oscillators.
Abstract: An ultra-low power clock reference generator has been developed using a 0.35-µm CMOS parameters. The circuit is based on a simple frequency-locked loop technique with no inductors, quartz resonators, and MEMS oscillators. Theoretical analyses and measurement results showed that the clock frequency could be controlled over a frequency range of 20 kHz - 2 MHz. The circuit showed a temperature coefficient of 170 ppm/˚C, a line regulation of 1%/V, and a power dissipation of 3µW, when operated at 200 kHz. A process sensitivity (σ/µ) was 5% without calibration technique. The proposed clock generator can be used as a reference clock for intermittent operation for use in subthreshold-operated, power-aware LSIs.
TL;DR: In this article, a self-biasing circuit based on a thermosensing CMOS circuit that changes its internal voltage steeply at a critical temperature was developed, which can be used as over-temperature and over-current protectors for LSI circuits.
Abstract: A thermosensing CMOS circuit that changes its internal voltage steeply at a critical temperature was developed. The circuit is based on a self-biasing circuit technique and uses the temperature-sensitive characteristics of MOSFETs operating in the subthreshold region. To develop this sensor device, a method to analyze self-biasing circuits, which is different from a conventional one, was employed. This method is useful for understanding the self-biasing circuit operation. A temperature sensor device makes use of a MOSFET resistor’s transition from a strong inversion to a weak-inversion or subthreshold operation. The temperature at which the transition occurs can be set to a desired value by adjusting the parameters of MOSFETs in the circuit. The sensor LSI can be made using a standard CMOS process and can be used as over-temperature and over-current protectors for LSI circuits. 2009 Institute of Electrical Engineers of Japan. Published by John Wiley & Sons, Inc.
TL;DR: A solid-state sensor that can detect the position of incident photons with a high spatial resolution is proposed and the results of Monte Carlo based computer simulations are demonstrated.
Abstract: This paper proposes a solid-state sensor that can detect the position of incident photons with a high spatial resolution. The sensor consists of a two-dimensional array of single-electron oscillators, each coupled to its neighbors through coupling capacitors. An incident photon triggers an excitatory circular wave of electron tunneling in the oscillator array. The wave propagates in all directions to reach the periphery of the array. By measuring the arrival time of the wave at the periphery, we can know the position of the incident photon. The tunneling wave's generation, propagation, arrival at the array periphery, and the determination of incident photon positions are demonstrated with the results of Monte Carlo based computer simulations.
01 Jan 2009
TL;DR: A model of an electric fish, Eigenmannia, that detects frequency differences between the individuals, on analog CMOS circuits that is equivalent to a conventional CMOS frequency comparator, although less post-processing is still required.
Abstract: In this paper, we implement a model of an electric fish, Eigenmannia, that detects frequency differences between the individuals, on analog CMOS circuits. The circuit’s fundamental function is equivalent to a conventional CMOS frequency comparator, although less post-processing is still required. The circuit consists of P- and T-units each of which encodes amplitudes and phases of the monitored electronic signals, respectively. Using a simulation program of integrated circuit emphasis (SPICE), we demonstrate that the proposed circuit can detect the phase difference effectively.
01 Jan 2009
TL;DR: This paper proposes a CMOS analog circuit implementing the VOR network that exploits non-uniformity of real MOS devices and shows that the output’s fidelity to the input pulses is certainly improved by the multiple neuron circuits where the non- uniformity is naturally embedded into the devices.
Abstract: Abstract—Recently, Hospedales et al. proposed a neural network model of “vestibulo-ocular reflex” (VOR) where a common input was given to multiple (nonidentical) spiking neurons accepting uncorrelated temporal noises, and the output was represented by the sum of the neurons’ outputs. Although the function of the VOR network is equivalent to pulse-density modulation, the neurons’ nonuniformity and temporal noises given to the neurons certainly improved the output spike’s fidelity to the analog input. In this paper, we propose a CMOS analog circuit implementing the VOR network that exploits non-uniformity of real MOS devices. Through extensive laboratory experiments using discrete MOS devices, we show that the output’s fidelity to the input pulses is certainly improved by the multiple neuron circuits where the non-uniformity is naturally embedded into the devices.
TL;DR: A floating millivolt reference circuit to generate a PTAT current was developed by using MOSFETs operated in the sub-threshold region as discussed by the authors, and the total power consumption of the circuit was 1.3 μW.
Abstract: A floating millivolt reference circuit to generate a PTAT current was developed by using MOSFETs operated in the subthreshold region. The circuit generates a floating voltage of 10 mV. The variations in the reference are ±2.7 % in a temperature range from -20 to 100°C. The total power consumption of the circuit was 1.3 μW.
30 Jul 2009
TL;DR: The circuit operation of the proposed neural segmentation model with a network consisting of six oscillators is demonstrated and the effects of mismatch in the threshold voltage of transistors are explored, and it is demonstrated that the network was tolerant to mismatch.
Abstract: We previously proposed a neural segmentation model suitable for implementation with complementary metal-oxide-semiconductor (CMOS) circuits. The model consists of neural oscillators mutually coupled through synaptic connections. The learning is governed by a symmetric spike-timing-dependent plasticity (STDP). Here we demonstrate and evaluate the circuit operation of the proposed model with a network consisting of six oscillators. Moreover, we explore the effects of mismatch in the threshold voltage of transistors, and demonstrate that the network was tolerant to mismatch (noise).
01 Jan 2009
TL;DR: A neuromorphic electrical circuit that performs pulse-density modulation at high fidelity by using noises in electrical circuits to improve fidelity to input based on a neural network model proposed by Hospedaleset al.
Abstract: We designed a neuromorphic electrical circuit that performs pulse-density modulation at high fidelity by using noises in electrical circuits. We constructed a network circuit based on a neural network model proposed by Hospedaleset al [1]. They regarded that the neural network used for the “vestibulo-ocular reflex” (VOR) could respond to temporal signals whose frequencies were higher than the maximal firing frequency of a single neuron in a network. In other words, the network could increases fidelity to the input of the network. They reported that this characteristic could be achieved by implications of temporal and spatial noises in neurons. We use temporal and spatial noises of electrical circuits to improve fidelity to input based on their model. Multiple neuron circuits are connected in parallel, and temporal noises and spatial noises are artificially implemented to mimic environmental noises and devices mismatches in electrical circuits. Through circuit simulations, we demonstrate that our proposed circuit with noises can conduct a temporal signal whose frequency is higher than the frequency that a single neuron circuit can conduct.
18 Oct 2009
TL;DR: In this paper, the authors investigated the implications of static noises in a pulse-density modulator based on the Vestibulo-ocular Reflex model and constructed a simple neuromorphic circuit consisting of an ensemble of single-electron devices and confirmed that static noises played an important role in improving the fidelity with which neurons could encode signals whose input frequencies are higher than the intrinsic response frequencies of single neurons.
Abstract: We investigated the implications of static noises in a pulse-density modulator based on Vestibulo-ocular Reflex model We constructed a simple neuromorphic circuit consisting of an ensemble of single-electron devices and confirmed that static noises (heterogeneity in circuit parameters) introduced into the network indeed played an important role in improving the fidelity with which neurons could encode signals whose input frequencies are higher than the intrinsic response frequencies of single neurons Through Monte-Carlo based computer simulations, we demonstrated that the heterogeneous network could corectly encode signals with input frequencies as high as 1 GHz, twice the range for single (or a network of homogeneous) neurons
15 Dec 2009
TL;DR: Through Monte-Carlo based computer simulations, it is demonstrated that noises could enhance the fidelity with which the network could correctly encode signals with high input frequencies: a noisy network could operate over a wider input range that a single neuron or a network of homogeneous neurons.
Abstract: This paper discusses the implications of noises in a pulse-density modulation single-electron circuit based on Vestibulo-ocular Reflex model. The proposed circuit consists of an ensemble of single-electron integrate-and-fire neurons that encode the input voltage into pulses whose temporal density is proportional to the amplitude of the input. We confirmed that static noises (heterogeneity in circuit parameters) and dynamic noises (random firing) introduced into the network indeed played an important role in improving the fidelity with which the neurons could encode signals with input frequencies higher than the intrinsic response frequencies of single neurons or a network of neurons without noises. Through Monte-Carlo based computer simulations, we demonstrated that noises could enhance the fidelity with which the network could correctly encode signals with high input frequencies: a noisy network could operate over a wider input range that a single neuron or a network of homogeneous neurons.
01 Jul 2009
TL;DR: In this paper, a CMOS level shifter that operates as a dc-cut capacitor is proposed, which consists of a differential pair and a unity gain buffer connected to one input of the differential pair.
Abstract: A CMOS level shifter that operates as a dc-cut capacitor is proposed. This circuit consists of a differential pair and a unity-gain buffer connected to one input of the differential pair. The unity-gain buffer consists of a subthreshold-operated operational amplifier and operates very slowly. The circuit operates as a high-pass filter and transmits ac signals but cuts off a dc voltage level. Therefore it can be used to connect two analog circuits having different dc levels. The results for the simulation and fabrication of this level shifter circuit are described.
TL;DR: This work confirmed the operation of the circuit by using a SPICE simulation with a set of 0.35-μm standard CMOS parameters, and performed Monte Carlo simulations assuming process spread and device mismatch in all MOSFETs.
Abstract: In low-voltage CMOS digital circuits, the threshold voltage variation causes significant circuit performance fluctuation: we therefore propose on-chip process compensation techniques for such circuits. We used voltage reference circuits, that can monitor process variations. We confirmed the operation of the circuit by using a SPICE simulation with a set of 0.35-μm standard CMOS parameters, and we performed Monte Carlo simulations assuming process spread and device mismatch in all MOSFETs. SPICE simulation demonstrated that the process variations of digital circuits were improved by 45% after applying the proposed architecture. These techniques will be useful for the on-chip process compensation of low-voltage digital circuits.
14 Jun 2009
TL;DR: It is demonstrated that the proposed circuit possesses noise-shaping characteristics, where signal and noises are separated into low and high frequency bands respectively, which significantly improved the signal-to-noise ratio (SNR) by 4.34 dB in the coupled network, as compared to the uncoupled one.
Abstract: We propose a bio-inspired circuit performing pulse-density modulation with single-electron devices. The proposed circuit consists of three single-electron neuronal units, receiving the same input and are connected to a common output. The output is inhibitorily fedback to the three neuronal circuits through a capacitive coupling, tuned to obtain a winners-share-all network operation. The circuit performance was evaluated through Monte-Carlo based computer simulations. We demonstrated that the proposed circuit possesses noise-shaping characteristics, where signal and noises are separated into low and high frequency bands respectively. This significantly improved the signal-to-noise ratio (SNR) by 4.34 dB in the coupled network, as compared to the uncoupled one. The noise-shaping properties are as a result of i) the inhibitory feedback between the output and the neuronal circuits, and ii) static noises (originating from device fabrication mismatches) and dynamic noises (as a result of thermally induced random tunneling events) introduced into the network.
01 Jan 2009
TL;DR: It is theoretically proved that a new type of stochastic resonance where nonzero receptive field size has maximal correlation between the subthreshold inputs and outputs occurs in the retinomorphic model proposed in [1] in this paper.
Abstract: We proposed a retinomorphic neural network model in [1] and through simulations observed a new type of stochastic resonance where nonzero receptive field size has maximal correlation between the subthreshold inputs and outputs. We theoretically prove that this kind of stochastic resonance occurs in the retinomorphic model proposed in [1] in this paper. We discuss several constraints to derive a theoretical equation that explains this phenomenon and show that not only certain noises intensity provide the optimal performance of signal detection but also nonzero receptive field size is a factor as well.
TL;DR: In this paper, a voltage-controlled oscillator (VCO) tolerant to process variations at lower supply voltage was proposed, which consists of an on-chip threshold-voltage monitor, a current-source circuit, a body-biasing control circuit, and the delay cells of the VCO.
Abstract: SUMMARY A voltage-controlled oscillator (VCO) tolerant to process variations at lower supply voltage was proposed. The circuit consists of an on-chip threshold-voltage-monitoring circuit, a current-source circuit, a body- biasing control circuit, and the delay cells of the VCO. Because variations in low-voltage VCO frequency are mainly determined by that of the current in delay cells, a current-compensation technique was adopted by using an on-chip threshold-voltage-monitoring circuit and body-biasing circuit techniques. Monte Carlo SPICE simulations demonstrated that variations in the oscillation frequency by using the proposed techniques were able to be suppressed about 65% at a 1-V supply voltage, compared to frequencies with and without the techniques.