Journal of Applied physics,Vol.33 : 1962年に発表されたレオロジー関連の論文

(IEEE Transactions on Electron Devices,36(12):2816-2820)Field-Drifting Resonant Tunneling Through a-Si:H/a-Sil-xCx:H Quantum Wells at Different Locations of the i-Layer of a p-i-n Structure

Spin-transfer torque magnetic tunnel junction (MTJ) is a promising candidate for nonvolatile memories thanks to its high speed, low power, infinite endurance, and easy integration with CMOS circuits. However, a relatively high current flowing through an MTJ is always required by most of the switching mechanisms, which results in a high electric field in the MTJ and a significant self-heating effect. This may lead to the dielectric breakdown of the ultrathin ( $\sim 1$ nm) oxide barrier in the MTJ and cause functional errors of hybrid CMOS/MTJ circuits. This paper analyzes the physical mechanisms of time-dependent dielectric breakdown (TDDB) in an oxide barrier and proposes an SPICE-compact model of the MTJ. The simulation results show great consistency with the experimental measurements. This model can be used to execute a more realistic design according to the constraints obtained from simulation. The users can estimate the lifetime, the operation voltage margin, and the failure probability caused by TDDB in the MTJ-based circuits.

Compact Model of Dielectric Breakdown in Spin-Transfer Torque Magnetic Tunnel Junction

多数の減磁曲線を用いた残留法における有限要素法の解(IEEE Transactions on Magnetics,24-1,1988)

The field of spintronics has attracted tremendous attention recently owing to its ability to offer a solution for the present-day problem of increased power dissipation in electronic circuits while scaling down the technology. Spintronic-based structures utilize electron’s spin degree of freedom, which makes it unique with zero standby leakage, low power consumption, infinite endurance, a good read and write performance, nonvolatile nature, and easy 3D integration capability with the present-day electronic circuits based on CMOS technology. All these advantages have catapulted the aggressive research activities to employ spintronic devices in memory units and also revamped the concept of processing-in-memory architecture for the future. This review article explores the essential milestones in the evolutionary field of spintronics. It includes various physical phenomena such as the giant magnetoresistance effect, tunnel magnetoresistance effect, spin-transfer torque, spin Hall effect, voltage-controlled magnetic anisotropy effect, and current-induced domain wall/skyrmions motion. Further, various spintronic devices such as spin valves, magnetic tunnel junctions, domain wall-based race track memory, all spin logic devices, and recently buzzing skyrmions and hybrid magnetic/silicon-based devices are discussed. A detailed description of various switching mechanisms to write the information in these spintronic devices is also reviewed. An overview of hybrid magnetic /silicon-based devices that have the capability to be used for processing-in-memory (logic-in-memory) architecture in the immediate future is described in the end. In this article, we have attempted to introduce a brief history, current status, and future prospectus of the spintronics field for a novice.

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Spintronic devices: a promising alternative to CMOS devices

Magnetic tunnel junction nanopillar with interfacial perpendicular magnetic anisotropy (PMA-MTJ) becomes a promising candidate to build up spin transfer torque magnetic random access memory (STT-MRAM) for the next generation of non-volatile memory as it features low spin transfer switching current, fast speed, high scalability, and easy integration into conventional complementary metal oxide semiconductor (CMOS) circuits. However, this device suffers from a number of failure issues, such as large process variation and tunneling barrier breakdown. The large process variation is an intrinsic issue for PMA-MTJ as it is based on the interfacial effects between ultra-thin films with few layers of atoms; the tunneling barrier breakdown is due to the requirement of an ultra-thin tunneling barrier (e.g., <1 nm) to reduce the resistance area for the spin transfer torque switching in the nanopillar. These failure issues limit the research and development of STT-MRAM to widely achieve commercial products. In this paper, we give a full analysis of failure mechanisms for PMA-MTJ and present some eventual solutions from device fabrication to system level integration to optimize the failure issues.

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Failure Analysis in Magnetic Tunnel Junction Nanopillar with Interfacial Perpendicular Magnetic Anisotropy.

Benefiting from its simple switching scheme (only a bidirectional current source), high-speed and low-power spin-transfer torque (STT) has been regarded as one of the most promising switching mechanisms for a magnetic tunnel junction (MTJ)-based non-volatile memory and logic circuits. However, it suffers from a number of reliability issues like write error induced by its intrinsic stochasticity, process variation, and so on. In order to reduce the write error rate, the mainstream solution is to enlarge the write pulse duration at the expense of write energy dissipation. Some self-terminated write circuits have been proposed to avoid the wasted write energy. But the hardware cost of these write circuits is especially large. In this paper, a novel cost-efficient self-terminated write circuit is proposed using two simple built-in sensing circuits. The proposed write circuit is simulated with a physics-based STT-MTJ compact model and a commercial CMOS 40 nm design kit. The simulation result shows about 35% reduction of circuit area and 10% lower energy consumption in comparison with that in prior work. In addition, the Error-Free write operation under process variation of both the CMOS transistor and the STT-MTJ is achieved due to its large sense margin ( $\sim 320$ mV).

High-Speed, Low-Power, and Error-Free Asynchronous Write Circuit for STT-MRAM and Logic

Provided is a magnetic storage based on voltage control. An MTJ structure of the magnetic storage is based on perpendicular magnetic anisotropy, namely, PMA, and a tunneling barrier layer is added on the basis of a classical MTJ structure, wherein the classical MTJ structure is a three layer structure which comprises a free layer, a reference layer and a tunneling barrier layer. The MTJ structure of the magnetic storage is formed by a bottom electrode, an antiferromagnetic metal mixing layer, first ferromagnetic metal, first oxide, second ferromagnetic metal, second oxide and a top electrode from bottom to top. The magnetic storage based on the voltage control has the advantages of being stable in nonvolatility, high in reading and writing speed, infinite in reading and writing times and the like. Due to the fact that magnetization states of storage units are changed based on the voltage control, electric currents needed for changing the states of the storage units are low, high reading and writing speed is maintained, and meanwhile low power consumption and a high power consumption utilization rate are achieved.

Magnetic storage based on voltage control

Traditional memory and logic gates are suffering the dilemma of power dissipation rising when the CMOS technology scales down to 40 nm node. By integrating the spin property of electrons, spintronics becomes an emerging technology to overcome definitively this bottleneck. In particular, the magnetic tunnel junction (MTJ) nanopillar combining with spin transfer torque (STT) switching mechanism has become a promising candidate to build novel low power integrated circuits thanks to its fast access speed, no-volatility and infinite endurance. This paper will describe the principle of STT and review its recent development for memories and logic gates. Related performance comparisons and physical challenges will be also outlined and discussed.

Spin transfer torque memories and logic gates

Magnetic memory stores data by magnetic state. It provides non-volatility, fast write/read speed and infinite endurance. Currently, the data-writing approach for magnetic memory is based on the spin transfer torque effect. However, a relatively large current is needed to change the magnetic state, which would cause high power dissipation and poor scaling performance. The solution to relieve these problems is a new data-writing approach based on voltage control. A new structure of this approach with higher storage density and better energy efficiency for the magnetic memory is studied, which makes it a strong competitor among the non-volatile memories.

Yu Zhang

Papers

Failure Analysis in Magnetic Tunnel Junction Nanopillar with Interfacial Perpendicular Magnetic Anisotropy.

High-Speed, Low-Power, and Error-Free Asynchronous Write Circuit for STT-MRAM and Logic

Magnetic storage based on voltage control

Spin transfer torque memories and logic gates

Design of a new voltage-controlled magnetic memory