This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

This paper reviews the fundamentals and latest progress of modeling, analysis, and design technologies for signal integrity and electromagnetic compatibility on PCB and package in the past decades. Most results in this field are based on the very rich and highly educational literature produced by Prof. C. Paul in his long scientific career. The inclusion of parameters variability effects is also considered, and it is demonstrated how statistical simulations can become affordable by means of recently-introduced stochastic methods. Finally, the necessity of practical training of designers is mentioned, and an experience relying on realistic PCB demonstrators is illustrated.

Overview of Signal Integrity and EMC Design Technologies on PCB: Fundamentals and Latest Progress

In three-dimensional integrated circuit (3D-IC) systems that use through-silicon via (TSV) technology, a significant design consideration is the coupling noise to or from a TSV. It is important to estimate the TSV noise transfer function and manage the noise-tolerance budget in the design of a reliable 3D-IC system. In this paper, a TSV noise coupling model is proposed based on a three-dimensional transmission line matrix method (3D-TLM). Using the proposed TSV noise coupling model, the noise transfer functions from TSV to TSV and TSV to the active circuit can be precisely estimated in complicated 3D structures, including TSVs, active circuits, and shielding structures such as guard rings. To validate the proposed model, a test vehicle was fabricated using the Hynix via-last TSV process. The proposed model was successfully verified by frequency- and time-domain measurements. Additionally, a noise isolation technique in 3D-IC using a guard ring structure is proposed. The proposed noise isolation technique was also experimentally demonstrated; it provided -17 dB and -10dB of noise isolation between the TSV and an active circuit at 100 MHz and 1 GHz, respectively.

Modeling and Analysis of Through-Silicon Via (TSV) Noise Coupling and Suppression Using a Guard Ring

The impedance of a power-distribution network (PDN) in three-dimensionally stacked chips with multiple through-silicon-via (TSV) connections (a 3D TSV IC) was modeled and analyzed using a power/ground (P/G) TSV array model based on separated P/G TSV and chip-PDN models at frequencies up to 20 GHz. The proposed modeling and analysis methods for the P/G TSV and chip-PDN are fundamental for estimating the PDN impedances of 3D TSV ICs because they are composed of several chip-PDNs and several thousands of P/G TSV connections. Using the proposed P/G TSV array model, we obtained very efficient analyses and estimations of 3D TSV IC PDNs, including the effects of TSV inductance and multiple-TSV inductance, depending on P/G TSV arrangement and the number of stacked chip-PDNs of a 3D TSV IC PDN. Inductances related to TSVs, combined with chip-PDN inductance and capacitance, created high upper peaks of PDN impedance, near 1 GHz. Additionally, the P/G TSV array produced various TSV array inductance effects on stacked chip-PDN impedance, according to their arrangement, and induced high PDN impedance, over 10 GHz.

PDN Impedance Modeling and Analysis of 3D TSV IC by Using Proposed P/G TSV Array Model Based on Separated P/G TSV and Chip-PDN Models

This paper describes a low-noise phase-locked loop (PLL) design method to achieve minimum jitter from a given PLL circuit topology. An optimal loop-bandwidth design method, derived from a discrete-time PLL model, further improves the jitter characteristics of a PLL already somewhat enhanced by optimizing individual circuit components. The described method not only estimates the timing jitter of a PLL, but also finds the optimal bandwidth minimizing the overall PLL jitter. A prototype PLL fabricated in a 0.6-/spl mu/m CMOS technology is tested. The measurement shows significant performance improvement by using the proposed method, The measured rms and peak-to-peak jitter of the PLL at the optimal loop-bandwidth are 3.1 and 22 ps, respectively.

(A) low noise phase-locked loop design by loop bandwidth optimization = 루프 대역의 최적화에 의한 저 잡음 PLL 설계

In this paper, a new modeling method for estimating the impedance properties in a chip-package hierarchical power distribution network (PDN) is proposed. The key ideas of the proposed modeling method are to decompose the chip-package hierarchical PDN into several structures, independently calculate the decomposed structures, and extract the whole structure's impedance by using a segmentation method. For the impedance calculations of the independently decomposed structures, a new method based on proposed analytic expressions is introduced for a chip level PDN, a resonant cavity model is used for a package level PDN, and equivalent circuit models are used for interconnections. The proposed method has been successfully verified by comparisons with measurements using a fabricated test vehicle in the frequency domain range up to 20 GHz, and it shows improved accuracy as well as computational superiority compared to EM simulations. Finally, the impedance properties in a chip-package hierarchical PDN are thoroughly investigated and analyzed.

Chip-Package Hierarchical Power Distribution Network Modeling and Analysis Based on a Segmentation Method

In this paper, we propose a compact and wideband electromagnetic bandgap (EBG) structure using a defected ground structure (DGS) to significantly enhance the wideband suppression of power/ground noise coupling in multilayer packages and printed circuit boards. The proposed EBG structure is implemented simply by adding a rectangular-shaped DGS which is etched periodically onto the ground plane without changing any other geometrical parameter from a mushroom-type EBG structure. The DGS effects on the fL and fU are thoroughly analyzed using the dispersion characteristics. We experimentally verified that the proposed EBG structure achieved the wideband power/ground noise suppression (below -40 dB) between 2.5 and 16.2 GHz. In addition, we demonstrated the considerable reduction in fL from 3.4 to 2.5 GHz and a significant increase in fU from 9.1 to 16.2 GHz when compared with the mushroom-type EBG structure.

A Compact and Wideband Electromagnetic Bandgap Structure Using a Defected Ground Structure for Power/Ground Noise Suppression in Multilayer Packages and PCBs

In this paper, a model of power supply noise (PSN) effects on an analog-to-digital converter (ADC) in a hierarchical structure is proposed. The ADC performance is determined by not only on-chip characteristics but also off-chip characteristics. Therefore, chip-package-printed circuit board (PCB) coanalysis and comodeling are required to accurately evaluate the performance of the ADC. We propose the comodel which allows the estimation and analysis of PSN effects on the ADC including off-chip characteristic. The proposed model includes three separate submodels: a power distribution network (PDN) model from the power/ground of the PSN source to the ADC power/ground, an on-chip circuit model from the ADC power/ground to the ADC inputs, and an ADC behavioral model from the ADC inputs to the factor of the effective number of bits (ENOB), which is one of the ADC performance factors. By applying a segmentation method for the PDN model, an analytical model for the on-chip circuit model, and a MATLAB model for the ADC behavioral model, fast, precise, and broadband estimations of the PSN effects are achieved. To validate the proposed models, an ADC was fabricated by a 0.13-μm CMOS process and wire bonded to the designed PCB. The ENOB of the ADC was measured by sweeping the PSN's frequency from 1 MHz up to 3 GHz, which was injected into the PCB to discover which noise frequency is critical to an ADC designed with a chip-PCB hierarchical structure. The results estimated by the proposed model correlated well with the cosimulated and measured results. The proposed modeling procedure saves the chip, package, and PCB designers time and computation resources to achieve high-quality analog devices or mixed-mode systems and provides an intuitive understanding of the noise effect.

Modeling and Measurement of Power Supply Noise Effects on an Analog-to-Digital Converter Based on a Chip-PCB Hierarchical Power Distribution Network Analysis

As data rate of serial interface has increased dramatically, timing margin has gotten tighter and tighter. Supply voltage has also kept deducing according to silicon process technology. However, supply noise is hardly reduced due to higher data rate, a huge number of transistors and slower improvement of packaging technology. Therefore, the jitter due to supply noise can be quite large compared to other jitter components. The jitter due to supply noise is not cancelled out by CDR or PLL at the receiver since PDN resonance frequency is higher than loop bandwidth of CDR or PLL. It is not cost effective if only PDN improvement is adopted to reduce supply noise induced jitter. It is essential to optimize performance at architecture level including circuits and PDN. In this paper, the new technique is proposed to minimize supply noise induced jitter in high speed serial interface. The proposed techniques called Jitter Equalizer (JEqualizer) improves jitter performance by 80% with minimal power increase and area over head. The impact is evaluated by supply noise induced jitter modeling.

A jitter equalization technique for minimizing supply noise induced jitter in high speed serial links

A new hybrid modeling method is proposed for the chip-package co-modeling and co-analysis. This method is designed to investigate the simultaneous switching noise (SSN) coupling paths and effects on the dc output voltage offset of the operational amplifier (OpAmp). It combines an analytical model of the circuit with a power distributed network (PDN) and interconnection models at the chip and package substrate. In order to validate the proposed model, CMOS OpAmp was fabricated using TSMC 0.25 mum. Then the dc output offset voltage of the OpAmp was measured by sweeping the SSN frequency from 10 MHz up to 3 GHz. It was successfully demonstrated that the experimental results are consistent with the predictions generated using the proposed model. We also confirmed that the dc offset voltage is strongly dependent on the SSN frequency and the PDN impedance profile of the chip-package hierarchical PDN. It shows the necessity for the chip-package co-modeling and simulation of the system-in-package designs.

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Yujeong Shim

Papers

Chip-Package Hierarchical Power Distribution Network Modeling and Analysis Based on a Segmentation Method

A Compact and Wideband Electromagnetic Bandgap Structure Using a Defected Ground Structure for Power/Ground Noise Suppression in Multilayer Packages and PCBs

Modeling and Measurement of Power Supply Noise Effects on an Analog-to-Digital Converter Based on a Chip-PCB Hierarchical Power Distribution Network Analysis

A jitter equalization technique for minimizing supply noise induced jitter in high speed serial links

Modeling and Analysis of Simultaneous Switching Noise Coupling for a CMOS Negative-Feedback Operational Amplifier in System-in-Package