Journal of Scientific Instruments Editor: Dr H R Lang Vol 28 and Supplement No 1, 1951 Pp xvi + 388 + iii + 80 (London: Institute of Physics, 1951) Bound, £3 12s; unbound, £3

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A Review of Scientific Instruments

Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new class of memory technologies and scaling of scientific procedures based on an investigation of recent progress in advanced Flash memory devices.

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Overview of emerging nonvolatile memory technologies

I-CYP binding sites) was determinedafter 24 hours of isoproterenol treatment and ex-pressed as the percentage of receptor number as-sessed in nonstimulated cells. Where necessary,MG132 (20 mM) or lactacystin (20 mM) mixed inserum-free media was added to cells 1 hour beforestimulation.16. P. van Kerkhof, R. Govers, C. M. Alves dos Santos, G. J.Strous,

https://cml.harvard.edu/assets/science294_1313.pdf

Logic Gates and Computation from Assembled Nanowire Building Blocks

As the dominating CMOS technology is fast approaching a "brick wall," new opportunities arise for competing solutions. Nanoelectronics has achieved several breakthroughs lately and promises to overcome many of the limitations intrinsic to current semiconductor approaches. Most of the results in this area reported until now focus on devices and interconnect; this work goes several steps further and presents issues related to circuits and architecture. Based on proposed nanoscale interconnect and device structures, we explore the design space available to the nanoelectronic circuit designer and system architect.

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Molecular electronics: from devices and interconnect to circuits and architecture

http://cmliris.harvard.edu/assets/science291_851.pdf

Functional Nanoscale Electronic Devices Assembled Using Silicon Nanowire Building Blocks

In this study, the possibility of compact modeling in single-electron circuit simulation has been investigated. It is found that each Coulomb island in single-electron circuits can be treated independently when the interconnections between single-electron transistors are large enough and a quantitative criterion for this condition is given. It is also demonstrated that, in those situations, SPICE macromodeling of single-electron transistors can be used for efficient circuit simulation. The developed macromodel produces simulation results with reasonable accuracy and with orders of magnitude less CPU time than usual Monte Carlo simulations.

Macromodeling of single-electron transistors for efficient circuit simulation

Falls are a serious medical and social problem among the elderly. This has led to the development of automatic fall-detection systems. To detect falls, a fall-detection algorithm that combines a simple threshold method and hidden Markov model (HMM) using 3-axis acceleration is proposed. To apply the proposed fall-detection algorithm and detect falls, a wearable fall-detection device has been designed and produced. Several fall-feature parameters of 3-axis acceleration are introduced and applied to a simple threshold method. Possible falls are chosen through the simple threshold and are applied to two types of HMM to distinguish between a fall and an activity of daily living (ADL). The results using the simple threshold, HMM, and combination of the simple method and HMM were compared and analyzed. The combination of the simple threshold method and HMM reduced the complexity of the hardware and the proposed algorithm exhibited higher accuracy than that of the simple threshold method.

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Fall-Detection Algorithm Using 3-Axis Acceleration: Combination with Simple Threshold and Hidden Markov Model

Monolithic 3D ICs (M3D) are an emerging technology that offers an ultra-high-density 3D integration due to the extremely small size of monolithic inter-tier vias. We explore various design styles available in M3D and present design techniques to obtain GDSII-level signoff quality results for each of these styles. We also discuss various challenges facing each style and provide solutions to them.

http://www.gtcad.gatech.edu/www/papers/jicce-2.pdf

Design challenges and solutions for ultra-high-density monolithic 3D ICs

On the basis of 2-D potential analysis performed while taking into account the effective conducting path effect, a new analytical model for threshold voltage in cylindrical surrounding-gate MOSFETs (SGMOSFETs) that contain localized charges is presented. From the 2-D Poisson's equation based on a parabolic potential approximation, a simple and accurate analytical expression for the threshold voltage is derived. The proposed model is validated using a 3-D device simulator, and good agreement is obtained for various device dimensions and charge distributions. This model can be used to investigate hot-carrier-induced degradation of SGMOSFETs.

Analytical Threshold Voltage Model Including Effective Conducting Path Effect (ECPE) for Surrounding-Gate MOSFETs (SGMOSFETs) With Localized Charges

An analytical current model unifying the n- and p-type accumulation-mode (junctionless) long-channel surrounding-gate nanowire field-effect transistors (AM-SGNW FETs), which is valid from low- to high-doping concentrations, is presented in this brief. A well-known continuous charge model derived by applying the parabolic potential approximation to the Poisson equation in a cylindrical coordinate system was used. The threshold voltage model is newly derived from the decoupled charge method to validate from low- to high-doping region. The simulation results obtained from the proposed charge and drain current model for the AM-SGNWFET agree well with those obtained from 3-D device simulation.

Yun Seop Yu

Papers

Macromodeling of single-electron transistors for efficient circuit simulation

Fall-Detection Algorithm Using 3-Axis Acceleration: Combination with Simple Threshold and Hidden Markov Model

Design challenges and solutions for ultra-high-density monolithic 3D ICs

Analytical Threshold Voltage Model Including Effective Conducting Path Effect (ECPE) for Surrounding-Gate MOSFETs (SGMOSFETs) With Localized Charges

A Unified Analytical Current Model for N- and P-Type Accumulation-Mode (Junctionless) Surrounding-Gate Nanowire FETs