In this paper, we explore the scaling limits of alternative gate dielectrics based on their direct-tunneling characteristics and gate-leakage requirements for future CMOS technology generations. Important material parameters such as the tunneling effective mass are extracted from the direct-tunneling characteristics of several promising high-/spl kappa/ gate dielectrics for the first time. We also introduce a figure-of-merit for comparing the relative advantages of various gate dielectrics based on the gate-leakage current. Using an accurate direct-tunneling gate-current model and specifications from the International Technology Roadmap for Semiconductors (ITRS), we provide guidelines for the selection of gate dielectrics to satisfy the projected off-state leakage current requirements of future high-performance and low-power technologies.

MOSFET gate leakage modeling and selection guide for alternative gate dielectrics based on leakage considerations

Atomic layer deposition (ALD) Al2O3 is a high-quality gate dielectric on III-V compound semiconductor with low defect density, low gate leakage, and high thermal stability. The high-quality of Al2O3∕InGaAs interface surviving from high temperature annealing is verified by excellent capacitance-voltage (CV) curves showing sharp transition from depletion to accumulation with “zero” hysteresis, 1% frequency dispersion per decade at accumulation capacitance, and strong inversion at split CV measurement. An enhancement-mode n-channel InGaAs metal-oxide-semiconductor field-effect-transistor is also demonstrated by forming true inversion channel at Al2O3∕InGaAs interface.

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Capacitance-voltage studies on enhancement-mode InGaAs metal-oxide-semiconductor field-effect transistor using atomic-layer-deposited Al2O3 gate dielectric

The write/erase characteristics of Germanium nanocrystal memory device are modeled using single-charge tunneling theory with quantum confinement and Coulomb blockade effects. A trap model is proposed to describe the retention characteristic of the nanocrystal memory. The impact of nanocrystal size, tunnel-oxide thickness, and high-k tunnel material is studied, and the suitability of the nanocrystal memory devices for nonvolatile memory and DRAM applications is discussed. Issues related to the scaling limit of the nanocrystal memory device are investigated.

Impact of crystal size and tunnel dielectric on semiconductor nanocrystal memory performance

Flash memory is the most widely used non-volatile memory device nowadays. In order to keep up with the demand for increased memory capacities, flash memory has been continuously scaled to smaller and smaller dimensions. The main benefits of down-scaling cell size and increasing integration are that they enable lower manufacturing cost as well as higher performance. Charge trapping memory is regarded as one of the most promising flash memory technologies as further down-scaling continues. In addition, more and more exploration is investigated with high-k dielectrics implemented in the charge trapping memory. The paper reviews the advanced research status concerning charge trapping memory with high-k dielectrics for the performance improvement. Application of high-k dielectric as charge trapping layer, blocking layer, and tunneling layer is comprehensively discussed accordingly.

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Review on Non-Volatile Memory with High-k Dielectrics: Flash for Generation Beyond 32 nm.

An interfacial self-cleaning phenomenon was found in the atomic layer deposition of HfO2 on In0.15Ga0.85As∕GaAs substrate using Hf(NCH3C2H5)4, i.e., TEMAH, and H2O as the precursors. The native oxides of InGaAs were all satisfactorily removed from the interface through ligand exchange (substitution) reactions with the TEMAH precursor. It relieves the Fermi-level pinning in the HfO2∕InGaAs heterostructure, as verified by the clear transition from accumulation to depletion in high-frequency capacitance-voltage relations and inversion in quasistatic measurement. A very low leakage current was also found from the metal-oxide-semiconductor capacitors of Au∕Ti∕HfO2∕InGaAs.

Interfacial self-cleaning in atomic layer deposition of HfO2 gate dielectric on In0.15Ga0.85As

The standard capacitance-voltage (C-V ) technique can no longer determine accurately the equivalent oxide thickness (EOT) for an advanced CMOS transistor with ultrathin gate dielectric where there is high gate leakage current, as well as series resistance; this situation will get worse as the CMOS transistor's scaling trend continues. This paper describes a simple methodology based on dual-frequency C-V measurement and four-element circuit model to extract accurately the EOT in the presence of gate leakage current and series resistance. This method can be effective with a current density of 1000 A/cm/sup 2/ for a 10 /spl mu/m /spl times/10 /spl mu/m capacitor. Such a high current density will satisfy the projected gate leakage current requirements for many generations of CMOS technologies, as specified in the 2003 International Technology Roadmap for Semiconductors.

A new method to extract EOT of ultrathin gate dielectric with high leakage current

High-quality jet vapor deposition nitride is investigated as a tunnel dielectric for flash memory device application. Compared to control devices with SiO/sub 2/ tunnel dielectric, faster programming speed as well as better retention time are achieved with low programming voltage. The p-channel devices can be programmed by hot electrons and erased by hot holes, or vice versa. Multilevel programming capability is shown.

JVD silicon nitride as tunnel dielectric in p-channel flash memory

— High-quality jet vapor deposition nitride is investi-gated as a tunnel dielectric for flash memory device application.Compared to control devices with SiO 2 tunnel dielectric, fasterprogramming speed as well as better retention time are achievedwith low programming voltage. The p-channel devices can be pro-grammed by hot electrons and erased by hot holes, or vice versa.Multilevel programming capability is shown.Index Terms— Charge injection, semiconductor memories, sil-icon nitride. I. I NTRODUCTION F LASH memory has the advantage of nonvolatility overDRAM, but has much slower program/erase speed andrequires higher operating voltages. In a conventional flashmemory device programmed by hot-electron injection, elec-trons must have energy close to or higher than that of the oxidebarrier (3.15 eV) to be injected into the floating gate. A verysmall percentage of electrons in the channel have such highenergy [1], so the current injected into the floating gate is verysmall, resulting in slow programming speed. High voltages arerequired to produce these hot electrons, so that it is difficult toscale the program/erase voltages with the technology node. Alow-barrier tunnel dielectric is necessary to improve program-ming efficiency and speed with the possibility of reducing theoperating voltages.Recently, jet vapor deposition (JVD) nitride has been demon-strated to be a promising high-quality gate dielectric for futureCMOS technologies [2] since it offers smaller gate-leakage cur-rent and reduced stress-induced leakage current compared toSiO gate dielectric. Due to its low barrier for electrons (2.12eV), JVD nitride can be used as the tunnel dielectric in a flashmemory device in order to enhance hot-electron injection andthereby improve the programming speed. Since the tunnelingbarrier for holes is only 1.9 eV, hot hole injection can be usedfor erasingwith appropriateoperatingvoltages.In thiswork, theperformance characteristics of the first p-channel flash memorydevices with JVD nitride tunnel dielectric are presented. Thep-channel flash memory devices offer several advantages overtheir n-channel counterparts: lower power, higher speed, and

JVD Silicon Nitride as Tunnel Dielectric in p-Channel

In this report we use vacuum ultraviolet spectroscopic ellipsometry (VUV‐SE) to determine the optical as well as structural properties of high‐k metal oxides, in particular, of hafnium aluminates and titanium aluminates grown by jet‐vapor deposition. In our opinion, the adapted approach employed in this study can be applied in most other high‐k dielectric thin films which are of great interest in developing a new material replacement for the SiO2 gate dielectric in CMOS and other IC devices. Specifically, VUV spectroscopic ellipsometry measurements were performed on a commercial ellipsometer with spectral range from 1.0 eV (1240 nm) to 8.7 eV (143 nm). The Generalized Tauc‐Lorentz (GTL) dispersion was used to determine the dielectric functions of these films. An ellipsometric model consisting of two layers of different film densities was found to be in excellent agreement with the experimental data. For the TiAlO films, only one film was needed in the model to fit the data. The optical bandgaps are seen to increase, while the relative film densities decrease, with increasing Al in the films. In addition, the optical dielectric functions shift to higher energy and decrease in magnitude as the films become more insulating. As a result, the Al appears to be mixed at the atomic level instead of forming a phase separation between HfO2 and Al2O3. For TiAlO, we observed similar results except that the fundamental optical bandgap was not strongly affected by the amount of Al incorporated in the films. In our opinion, the adapted approach employed in this study can be applied in most other high‐k dielectric thin films which are of great interest in developing a new material replacement for SiO2 in CMOS and other IC devices.

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Optical Properties of Jet-Vapor-Deposited TiAlO and HfAlO Determined by Vacuum Utraviolet Spectroscopic Ellipsometry

Methods of forming silicided contacts self-aligned to a gate from polysilicon germanium and a structure so formed are disclosed. One embodiment of the method includes: forming a polysilicon germanium (poly SiGe) pedestal over a gate dielectric over a substrate; forming a poly SiGe layer over the poly SiGe pedestal, the poly SiGe layer having a thickness greater than the poly SiGe pedestal; doping the poly SiGe layer; simultaneously forming a gate and a contact to each side of the gate from the poly SiGe layer, the gate positioned over the poly SiGe pedestal; annealing to drive the dopant from the gate and the contacts into the substrate to form a source/drain region below the contacts; filling a space between the gate and the contacts; and forming silicide in the gate and the contacts.

Zhijiong Luo

Papers

A new method to extract EOT of ultrathin gate dielectric with high leakage current

JVD silicon nitride as tunnel dielectric in p-channel flash memory

JVD Silicon Nitride as Tunnel Dielectric in p-Channel

Optical Properties of Jet-Vapor-Deposited TiAlO and HfAlO Determined by Vacuum Utraviolet Spectroscopic Ellipsometry

Forming silicided gate and contacts from polysilicon germanium and structure formed