Two-dimensional (2D) semiconductors have attracted tremendous interest as atomically thin channels that could facilitate continued transistor scaling. However, despite many proof-of-concept demonstrations, the full potential of 2D transistors has yet to be determined. To this end, the fundamental merits and technological limits of 2D transistors need a critical assessment and objective projection. Here we review the promise and current status of 2D transistors, and emphasize that widely used device parameters (such as carrier mobility and contact resistance) could be frequently misestimated or misinterpreted, and may not be the most reliable performance metrics for benchmarking 2D transistors. We suggest that the saturation or on-state current density, especially in the short-channel limit, could provide a more reliable measure for assessing the potential of diverse 2D semiconductors, and should be applied for cross-checking different studies, especially when milestone performance metrics are claimed. We also summarize the key technical challenges in optimizing the channels, contacts, dielectrics and substrates and outline potential pathways to push the performance limit of 2D transistors. We conclude with an overview of the critical technical targets, the key technological obstacles to the 'lab-to-fab' transition and the potential opportunities arising from the use of these atomically thin semiconductors.

Promises and prospects of two-dimensional transistors

The discovery of two-dimensional (2D) materials with unique electronic, superior optoelectronic, or intrinsic magnetic order has triggered worldwide interest in the fields of material science, condensed matter physics, and device physics. Vertically stacking 2D materials with distinct electronic and optical as well as magnetic properties enables the creation of a large variety of van der Waals heterostructures. The diverse properties of the vertical heterostructures open unprecedented opportunities for various kinds of device applications, e.g., vertical field-effect transistors, ultrasensitive infrared photodetectors, spin-filtering devices, and so on, which are inaccessible in conventional material heterostructures. Here, the current status of vertical heterostructure device applications in vertical transistors, infrared photodetectors, and spintronic memory/transistors is reviewed. The relevant challenges for achieving high-performance devices are presented. An outlook into the future development of vertical heterostructure devices with integrated electronic and optoelectronic as well as spintronic functionalities is also provided.

Van der Waals Heterostructures for High‐Performance Device Applications: Challenges and Opportunities

As a novel member of the two-dimensional nanomaterial family, mono- or few-layer black phosphorus (BP) with direct bandgap and high charge carrier mobility is promising in many applications such as microelectronic devices, photoelectronic devices, energy technologies, and catalysis agents. Due to its benign elemental composition (phosphorus), large surface area, electronic/photonic performances, and chemical/biological activities, BP has also demonstrated a great potential in biomedical applications including biosensing, photothermal/photodynamic therapies, controlled drug releases, and antibacterial uses. The nature of the BP-bio interface is comprised of dynamic contacts between nanomaterials (NMs) and biological systems, where BP and the biological system interact. The physicochemical interactions at the nano-bio interface play a critical role in the biological effects of NMs. In this review, we discuss the interface in the context of BP as a nanomaterial and its unique physicochemical properties that may affect its biological effects. Herein, we comprehensively reviewed the recent studies on the interactions between BP and biomolecules, cells, and animals and summarized various cellular responses, inflammatory/immunological effects, as well as other biological outcomes of BP depending on its own physical properties, exposure routes, and biodistribution. In addition, we also discussed the environmental behaviors and potential risks on environmental organisms of BP. Based on accumulating knowledge on the BP-bio interfaces, this review also summarizes various safer-by-design strategies to change the physicochemical properties including chemical stability and nano-bio interactions, which are critical in tuning the biological behaviors of BP. The better understanding of the biological activity of BP at BP-bio interfaces and corresponding methods to overcome the challenges would promote its future exploration in terms of bringing this new nanomaterial to practical applications.

Property-Activity Relationship of Black Phosphorus at the Nano-Bio Interface: From Molecules to Organisms

Two-dimensional crystals have emerged as a class of materials that may impact future electronic technologies. Experimentally identifying and characterizing new functional two-dimensional materials is challenging, but also potentially rewarding. Here, we fabricate field-effect transistors based on few-layer black phosphorus crystals with thickness down to a few nanometres. Reliable transistor performance is achieved at room temperature in samples thinner than 7.5 nm, with drain current modulation on the order of 10(5) and well-developed current saturation in the I-V characteristics. The charge-carrier mobility is found to be thickness-dependent, with the highest values up to ∼ 1,000 cm(2) V(-1) s(-1) obtained for a thickness of ∼ 10 nm. Our results demonstrate the potential of black phosphorus thin crystals as a new two-dimensional material for applications in nanoelectronic devices.

http://absimage.aps.org/image/MAR14/MWS_MAR14-2013-005031.pdf

Black Phosphorus Field-effect Transistors

Owing to their tunable direct bandgap, high charge carrier mobility, and unique in-plane anisotropic structure, black phosphorus nanosheets (BPNSs) have emerged as one of the most important candidates among the 2D materials beyond graphene. However, the poor ambient stability of black phosphorus limits its practical application, due to the chemical degradation of phosphorus atoms to phosphorus oxides in the presence of oxygen and/or water. Chemical functionalization is demonstrated as an efficient approach to enhance the ambient stability of BPNSs. Herein, various covalent strategies including radical addition, nitrene addition, nucleophilic substitution, and metal coordination are summarized. In addition, efficient noncovalent functionalization methods such as van der Waals interactions, electrostatic interactions, and cation-π interactions are described in detail. Furthermore, the preparations, characterization, and diverse applications of functionalized BPNSs in various fields are recapped. The challenges faced and future directions for the chemical functionalization of BPNSs are also highlighted.

/pdf/recent-advances-in-chemical-functionalization-of-2d-black-1ys7yl22ig.pdf

Recent Advances in Chemical Functionalization of 2D Black Phosphorous Nanosheets

As a strong candidate for future electronics, atomically thin black phosphorus (BP) has attracted great attention in recent years because of its tunable bandgap and high carrier mobility. Here, we show that the transport properties of BP device under high electric field can be improved greatly by the interface engineering of high-quality HfLaO dielectrics and transport orientation. By designing the device channels along the lower effective mass armchair direction, a record-high drive current up to 1.2 mA/μm at 300 K and 1.6 mA/μm at 20 K can be achieved in a 100-nm back-gated BP transistor, surpassing any two-dimensional semiconductor transistors reported to date. The highest hole saturation velocity of 1.5 × 107 cm/s is also achieved at room temperature. Ballistic transport shows a record-high 36 and 79% ballistic efficiency at room temperature and 20 K, respectively, which is also further verified by theoretical simulations.

https://advances.sciencemag.org/content/advances/5/6/eaau3194.full.pdf

High-speed black phosphorus field-effect transistors approaching ballistic limit.

In this paper, hot carrier degradation (HCD) in FinFET is studied for the first time from trap-based approach rather than conventional carrier-based approach, with full Vgs/Vds bias characterization and self-heating correction. New HCD time dependence is observed, which cannot be predicted by traditional models. A trap-based HCD compact model is proposed and verified in both n- and p-type FinFETs, which is unified across different Vgs/Vds regions with different carrier transport mechanisms. Impacts of HCD on analog circuits is also demonstrated, showing bias runaway effect. The results provide new insights of HCD in FinFET, which are helpful to circuit design for reliability.

New insights into the hot carrier degradation (HCD) in FinFET: New observations, unified compact model, and impacts on circuit reliability

Device variability and reliability are becoming increasingly important for nano-CMOS technology and circuits, due to the shrinking circuit design margin with the downscaling supply voltage (V dd ) Therefore, robust design should have the awareness of both variability and reliability In FinFET technology, strong correlation between the variations of device electrical parameters is found, due to the larger impacts of line-edge roughness (LER) in FinFET structure Accurate compact models and new design methodology for random variability in FinFETs were proposed for the variation-and correlation-aware design For the reliability awareness, the impacts of BTI-induced temporal shift and the layout dependent aging effects should be taken into account for the optimization of end-of-life (EOL) performance/power/area (PPA) New-generation aging model and circuit reliability simulator for FinFETs were proposed and developed in industry-standard EDA tools Future challenges are also pointed out, such as statistical BTI and RTN The results are helpful for the robust and resilient design for 16/14nm and beyond

Variability-and reliability-aware design for 16/14nm and beyond technology

In this brief, typical locations of the interface and oxide traps generated by the hot carrier degradation (HCD) in FinFETs are studied with experiments and “atomistic” TCAD simulations under the worst case stress conditions. The typical round-Fin locations of different types of traps are analyzed by comparing the experimentally extracted results with the calibrated TCAD simulations. Then, the traps’ different impacts on HCD variations in both forward and reverse bias modes are employed to disclose the typical lateral locations of different traps. The results suggest that for both n- and p-type of FinFETs under the worst case stress conditions, the interface traps and oxide traps (type 1) are mainly distributed in the midchannel region closer to the source side on the Fin side, whereas oxide traps (type 2) are mainly distributed in the midchannel region closer to the drain side on the Fin top. Therefore, the two types of oxide traps originate in the different generation locations but may share the same atomistic structures in the same device. The results are helpful to the physical understandings of HCD in the FinFET technology.

On the Trap Locations in Bulk FinFETs After Hot Carrier Degradation (HCD)

In this letter, the lateral trap distributions in planar and FinFET devices are experimentally studied under various bias stress conditions of hot-carrier degradation (HCD). In contrast to the traditional understanding that the generated traps are crowded near the drain region during hot-carrier stress, it is found that the peak of the trap distribution profile will gradually move closer to the source region with the increase in ${V}_{\text {ds}}$ stress. The results suggest that the electron–electron scattering and multiple vibrational excitation are important mechanisms for the lateral trap distributions during HCD stress, which is helpful for the physical understanding of HCD.

Zhuoqing Yu

Papers

High-speed black phosphorus field-effect transistors approaching ballistic limit.

New insights into the hot carrier degradation (HCD) in FinFET: New observations, unified compact model, and impacts on circuit reliability

Variability-and reliability-aware design for 16/14nm and beyond technology

On the Trap Locations in Bulk FinFETs After Hot Carrier Degradation (HCD)

Investigation on the Lateral Trap Distributions in Nanoscale MOSFETs During Hot Carrier Stress