Showing papers by "Zili Shao published in 2012"

Real-Time Flash Translation Layer for NAND Flash Memory Storage Systems

Abstract: Due to the variable garbage collection latency, NAND flash memory storage systems may suffer long system response time, especially when the flash memory is close to be full. Most of existing flash translation layer (FTL) schemes focus on improving the average response time but ignore to provide a desirable worst case response time upper bound. This paper proposes a Real-time Flash Translation Layer (RFTL) scheme to hide the long garbage collection latency while satisfying a worst case response time upper bound that achieves an ideal case. We achieve this by using a distributed partial garbage collection policy that enables RFTL to reclaim the space and to serve the write requests simultaneously. A new block-level address mapping approach is designed to guarantee enough free space to serve the write request arriving at any time period. Experimental results show that our scheme improves both the worst case system response time and the average system response time compared with previous work.

Utilizing PCM for Energy Optimization in Embedded Systems

Abstract: Due to its high density, bit alterability, and low standby power, phase change memory (PCM) is considered as a promising DRAM alternative. In embedded systems, especially battery-driven mobile devices, energy is one of the most important performance metrics. Therefore, it becomes an interesting problem of utilizing PCM for energy optimization in embedded systems. While recently there have been extensive studies on PCM, energy optimization with PCM in embedded systems has not been fully addressed. In this paper, we present a hybrid memory system architecture in which PCM is used to replace DRAM as much as possible so the system energy can be reduced by utilizing the lower standby power of PCM. However, to achieve this, system-level software optimization techniques are required in order to solve problems caused by the three disadvantages of PCM: namely, long write latency, large write energy and limited write endurance. We propose an optimal static data allocation scheme to solve a simplified problem, and discuss how to extend this to solve more complex problems. We also present emerging research issues in compiler optimization, real-time task scheduling and operating systems when utilizing PCM for energy optimization in embedded systems.

A Space Reuse Strategy for Flash Translation Layers in SLC NAND Flash Memory Storage Systems

Abstract: This paper presents a space reuse strategy for flash translation layers in SLC nand flash storage systems. The basic idea is to prevent a block with many free pages from being erased in a merge operation. The preserved blocks are further reused as replacement blocks. In such a way, the space utilization and the number of erase counts of each block in a nand flash are enhanced. By employing the reuse strategy, we propose a reuse-aware flash translation layer (FTL) called reuse-aware NFTL (RNFTL) to improve the endurance and space utilization of single level cell (SLC) nand flash. We provide the performance analysis of RNFTL for frequent update operations and sequential write operations, and theoretically compare RNFTL with representative FTL schemes. We also discuss the opportunity to apply the reuse strategy in log-block-based FTL schemes. To the best of our knowledge, this is the first work to employ a space reuse strategy in FTLs to improve the space utilization and endurance of nand flash. The experiments have been conducted on a set of traces collected from real workload in daily life. The results show that the space reuse strategy can effectively improve space utilization, block lifetime and wear-leveling compared with the previous work.

Staying-alive path planning with energy optimization for mobile robots

Abstract: Most mobile robots are powered by batteries, and their energy and operation time are limited. Therefore, how to minimize energy consumption and keep mobile robots to stay alive becomes an important problem. In this paper, we propose a staying-alive and energy-efficient path planning algorithm, SLEEP (Staying-aLive and Energy-Efficient Path planning), to solve this problem based on the Tabu-search method. In SLEEP, we consider both energy consumption and staying-alive for the path planning of rechargeable mobile robots. We design and implement our approach based on a real mobile robot platform, and conduct experiments in a real-life environment. The experimental results show that SLEEP can provide an effective path planning by which a robot can be guaranteed to stay alive and finish all tasks with the minimum energy.

3D-FlashMap: a physical-location-aware block mapping strategy for 3D NAND flash memory

Abstract: Three-dimensional (3D) flash memory is emerging to fulfil the ever-increasing demands of storage capacity. In 3D NAND flash memory, multiple layers are stacked to increase bit density and reduce bit cost of flash memory. However, the physical architecture of 3D flash memory leads to a higher probability of disturbance to adjacent physical pages and greatly increases bit error rates. This paper presents 3D-FlashMap, a novel physical-location-aware block mapping strategy for three-dimensional NAND flash memory. 3D-FlashMap permutes the physical mapping of blocks and maximizes the distance between consecutively logical blocks, which can significantly reduce the disturbance to adjacent physical pages and effectively enhance the reliability. We apply 3D-FlashMap to a representative flash storage system. Experimental results show that the proposed scheme can reduce uncorrectable page errors by 85% with less than 2% space overhead in comparison with the baseline scheme.

Meta-Cure: a reliability enhancement strategy for metadata in NAND flash memory storage systems

Abstract: The increasing density of NAND flash memory leads to a dramatic increase in the bit error rate of flash, which greatly reduces the ability of error correcting codes (ECC) to handle multi-bit errors. To ensure the functionality and reliability of flash memory, the pages containing address mapping information and other metadata should be carefully stored in flash memory. This paper presents Meta-Cure, a novel hardware and file system interface that transparently protects metadata in the presence of multi-bit faults. Meta-Cure exploits built-in ECC and replication in order to protect pages containing critical data. Redundant pairs are formed at run time and distributed to different physical pages to protect against failures. Meta-Cure requires no changes to the file system, on-chip hierarchy, or hardware implementation of flash memory chip. Experimental results show that the proposed technique can reduce uncorrectable page errors by 92% with less than 1% space overhead in comparison with conventional error correction techniques.

A block-level flash memory management scheme for reducing write activities in PCM-based embedded systems

Abstract: This paper targets at an embedded system with phase change memory (PCM) and NAND flash memory. Although PCM is a promising main memory alternative and is recently introduced to embedded system designs, its endurance keeps drifting down and greatly limits the lifetime of the whole system. Therefore, this paper presents a block-level flash memory management scheme, WAB-FTL, to effectively manage NAND flash memory while reducing write activities of the PCM-based embedded systems. The basic idea is to preserve each bit in flash mapping table hosted by PCM from being inverted frequently during the process of mapping table update. To achieve this, a new merge strategy is adopted in WAB-FTL to delay the mapping table update, and a tiny mapping buffer is used for caching frequently updated mapping records. Experimental results based on Android traces show that WAB-FTL can effectively reduce write activities when compared with the baseline scheme.

Optimally Maximizing Iteration-Level Loop Parallelism

Abstract: Loops are the main source of parallelism in many applications. This paper solves the open problem of extracting the maximal number of iterations from a loop to run parallel on chip multiprocessors. Our algorithm solves it optimally by migrating the weights of parallelism-inhibiting dependences on dependence cycles in two phases. First, we model dependence migration with retiming and formulate this classic loop parallelization into a graph optimization problem, i.e., one of finding retiming values for its nodes so that the minimum nonzero edge weight in the graph is maximized. We present our algorithm in three stages with each being built incrementally on the preceding one. Second, the optimal code for a loop is generated from the retimed graph of the loop found in the first phase. We demonstrate the effectiveness of our optimal algorithm by comparing with a number of representative nonoptimal algorithms using a set of benchmarks frequently used in prior work and a set of graphs generated by TGFF.

Write-activity-aware page table management for PCM-based embedded systems

Abstract: Due to its low power consumption and high density, phase change memory (PCM) becomes a promising main-memory alternative to DRAM in embedded systems. PCM, however, has the endurance problem in which the number of rewrites to each cell is quite limited compared with DRAM. Therefore, it is fundamental to eliminate unnecessary writes in PCM-based embedded systems. This paper presents a simple yet effective scheme to solve this problem, through redesigning existing software to exploit write-activity-aware features provided by underlying hardware. Particularly, we target at page table management, a key kernel component residing in the memory management part of the Linux kernel. We present for the first time a write-activity-aware page table management scheme, WAPTM, accomplished through two modifications to the page table initialization and page frame allocation process. The scheme has been implemented in Google Android 2.3 based on ARM architecture and evaluated with real applications on the Android emulator. The experimental results show that the proposed scheme can significantly reduce write activities to page tables in the new kernel compared with the original Android. We hope this work can serve as a first step towards the design of write-activity-aware operating systems via simple and feasible modifications.

PTL: PCM Translation Layer

Abstract: PCM (Phase Change Memory) has been used as NOR flash replacement in embedded systems, and poses interesting system-level challenges for transparent exploitation of these memory structures by embedded systems software. We propose such a system-level transparent framework, called PTL (PCM Translation Layer), to efficiently manage PCM. PTL's translation layer conceals the physical constraints of the PCM architecture so that embedded systems software can use PCMs in a transparent manner, while efficiently exploiting the idiosyncrasies of the PCM architecture. We study the requirements for transparently managing PCM in embedded systems, and propose the system architecture of PTL. As a case study, we propose a simple yet effective wear leaveling technique by exploiting application-specific features in embedded systems. The experimental results show that our wear leveling technique can effectively improve the lifetime of PCM chips compared with the previous work. We expect this work can serve as a first step towards the full exploration of PCM in embedded systems.