Showing papers presented at "Electrical Design of Advanced Packaging and Systems Symposium in 2022"

Fast Eye Diagram Simulation based on Latency Insertion Method

Abstract: Eye diagrams are used to assess the quality of high-speed channels. They are thus very important for signal integrity analysis. The voltage-in-current latency insertion method (VinC LIM) is a fast transient circuit simulation algorithm with superior stability properties. In this paper, VinC LIM is proven to be reliable for fast transient simulation of eye diagrams. The results and speed are compared with the transient simulation and channel simulation of commercial platforms.

Resonant subsurface terahertz absorber based on patterned graphene

Abstract: In this paper, we simulate and demonstrate a patterned graphene resonant subsurface terahertz absorber using the finite element method. By adjustment of the parameters of the geometry of the structure, the absorber’s absorption can be tuned well. The structure’s angle of incidence is also evaluated. The structure can be optimally tuned to achieve over 92% absorption at any frequency point in the 1.40 THz to 3.44 THz frequency band. The structure designed by introducing two-dimensional materials has promising applications in terahertz detection and sensing, and can also be used to make filter components.

A Novel Dualband Patch Antenna with Liquid Metal and Flexible Packaging for Strain Sensing

Abstract: This paper presents a novel microstrip patch antenna based on a Polydimethylsiloxane (PDMS) dielectric substrate and liquid metal for strain sensing applications. The dual broadband antenna operates from 1.0 GHz to 2.5 GHz for the strain sensing. Multi-physics field modeling and simulation are performed by the well-known software COMSOL and a linear numerical relationship between the resonant frequency and strain has been obtained. Base on the relationship, the antenna can be used as a strain sensor to detect the deformation of some structures from the change of resonant frequency.

Power Distribution Network Impedance Analysis considering Thermal Distribution

Abstract: In this paper, we analyzed a power distribution network (PDN) impedance considering thermal distribution. Due to the development of integrated circuits (ICs) towards high density and high performance, the supply voltage has been reduced while power density has been increased. Shrunk supply voltage causes a low voltage margin and high temperature caused by the high power density varies the circuit parameters of the PDN. Thus, considering the operating temperature effects for a robust PDN design is essential. However, the previous power integrity analysis is not focused on temperature effects on PDN. Hence, impedance analysis of PDN considering thermal distribution is essential. Therefore, this research analyzed thermal distribution effects on the self-impedance of PDN. By using a W-element model, we analyzed thermal distribution effects on PDN self-impedance by circuit simulation. As a result, the difference in self-impedances is observed between the PDNs with other thermal distributions in spite of current loop path and mean temperature; The capacitance has same value as the capacitance considering mean temperature of thermal distribution; The value of the resistance closes to the resistance considering the temperature at the probing point, not the mean temperature.

A Novel 3-D Frequency Selective Structure for Radiation Leakage Suppression in Sub-6G Highly Integrated Package

Abstract: This paper presents a novel three-dimensional frequency selective surface (3-D FSS) dedicated to highly integrated package in Sub-6G communication applications. The structure operates between 3.3 GHz and 3.8 GHz with two stopbands on each side. A stable response under the incident angles up to 50° is shown through an electromagnetic simulator analysis. The in-band insertion loss is less than 0.65 dB and the out-of-band insertion loss is more than 10 dB for both TE and TM polarizations under the incident angle up to 50°. Moreover, this novel structure is insensitive to all polarization and has a unit cell size of 0.07λ. All these results indicate that the proposed FSS is a good candidate for radiation leakage suppression in Sub-6G highly integrated package.

Design and Analysis of Hierarchical Power Distribution Network (PDN) for Full Wafer Scale Chip (FWSC) Module

Abstract: In this paper, we design and analyze the hierarchical power distribution network (PDN) for full wafer scale chip (FWSC) module. With its high bandwidth and low latency, FWSC has been considered a promising solution in the artificial intelligence (AI) processor market. However, the huge size of FWSC inevitably leads to long current paths and high impedance that consequently cause large IR drop and power/ground noise. In an effort to overcome these issues, the hierarchical PDN of FWSC module is designed in a 3D structure that allows direct interconnection from PCB to chip to minimize the current path. Although there are several studies related to PDN design for FWSC module, they conducted limited analysis on a specific PDN only. We design the hierarchical PDN for FWSC module composed of PCB PDN, multi-array silicone rubber socket (SRS)-based PDN, multi-array through wafer via (TWV)-based PDN, and on-chip PDN. Each PDN component was modeled into equivalent circuit models. Then, we fully analyzed the overall hierarchical PDN impedance in the frequency domain.

Tapered Differential Multibit Through Glass Vias for Three-Dimensional Integrated Circuits

Abstract: We present an electrical model of tapered differential-multibit through glass vias (DM-TGVs) for high density three-dimensional (3-D) integration. Analytical equations are developed to compute the impedance parasitics of tapered DM-TGVs. Simulations using the 3-D field solver with parameter modifications, such as slope angle of the TGV, type of filler material are used to confirm the scalability of the proposed model. We examine the electrical behavior of tapered TGVs in the frequency domain using the proposed model. Eye-diagram measurements are also used to verify the frequency dependent loss of capacitive-resistive TGV in the time domain.

Electromagnetic-Thermal Co-simulation of a Patch Antenna

Abstract: In order to simulate the influence of the thermal effects of a patch antenna on its electromagnetic radiation performance, the discontinuous Galerkin time domain (DGTD) method and finite element time domain (FETD) method are employed to implement electromagnetic-thermal co-simulation. The Maxwell equation is solved by DGTD method, while the heat conduction equation is solved by FETD method. The electromagnetic and thermal simulation are linked by loss power of material and temperature dependent conductivity. Numerical results show that the radiation pattern will change if we consider the thermal effects of the patch antenna.

IC Package with the system board Interconnects - simulation showing PDN noise due to simultaneous switching IOs and its effect on Signal Integrity

Abstract: The analysis of package design with the PCB interconnects presented here shows the benefit of signal and power integrity co-simulations with power aware approach to mitigate the signal degradation that are caused by non-ideal behavior of the power distribution network and the simultaneous switching I/Os.

A New Current Crowding Phenomenon for Flip-Chip-on-Leadframe (FCOL) Package and its Impact on Electromigration Reliability

Abstract: Electromigration (EM) is a critical problem for interconnect reliability of modern integrated circuits (ICs) packages. In flip-chip-on-leadframe (FCOL) package, a new current crowding phenomenon at the solder joints interface is observed that exacerbates the maximum current density. To address this recent phenomenon, in this work, we detail the mechanisms of the electric current paths that lead to a potential adjustment of the average current density parameter in the current Black’s mean time to failure (MTTF) mathematical model. An appropriate design-of-experiment (DOE) for the FCOL package is developed. Through extensive simulation via a 3D quasi-static solver, the potential impact of this new phenomenon is assessed and quantified. A 35% increase in maximum current density was observed under the worst-case condition. Implications of the findings for future high-density microelectronic is under investigation experimentally.

Power Integrity and Enablement Challenges for Integrated Dual-Mode Linear Voltage Regulator in Next Generation Intel® Core Microprocessor

Abstract: A dual mode digital power gate (PG) and linear low drop-out regulator (LDO) is implemented on Intel® next generation™ microprocessor to enable different IPs on the SoC to operate at their minimal voltage levels. This paper discusses post silicon debug and validation techniques to characterize an integrated dual-mode voltage regulator. Performance metrics such as mode transition, power saving, circuit stability and voltage droop are measured and established in this work. These techniques in general can be applied to an integrated linear voltage regulator. The regulated modes are used when load current or ∂i/∂t is low thus allowing better power management in deeper package core states. Measurement shows 11% power saving in the allocated power budget in PKGC10 when voltage regulator is enabled to regulate at 0.7volt output.

Passive Modeling of Interconnects Using Sum of Squares Partial Fraction Expansions

Abstract: Vector fitting has been successfully applied for signal and power integrity design of interconnects and power distribution networks. It is based on a partial fraction expansion of rational functions, resulting in a well-conditioned algorithm applicable to large size problems. A major shortcoming of vector fitting is that the resulting model in many cases will not be passive. In this paper we introduce a sum-of-squares (SOS) partial fraction passivity enforcement algorithm for fitting residues of a passive network. We demonstrate that this new algorithm provides a necessary and sufficient condition for passivity enforcement of scalar networks.

The Eccentrics of CPU FIVR AGS supply noise debug and learnings

Abstract: SoC design, validation, and manufacturing teams all need to work in tandem to ensure a successful product is released to the market. Pre-silicon and post-silicon validation is critical and is performed to ensure minimal Si re-spins at the fabrication and avoid any design bugs reaching the end customer. The post-silicon debug of various power failures issues related to analog supply exhibiting random signatures induced learnings that can help expedite changes in post-Si validation and high-volume screening, Discussed in detail are the debug efforts to identify one of the many Analog Generation Supply (AGS) noise failure and isolation. The paper elucidates reports of the proposed defects and their various bearings, issue root causes, and issue validation suite formation.

A Methodology to Optimize the Number and Placement of Decoupling Capacitors in a Multilevel Power Delivery Network

Abstract: It is increasingly challenging to satisfy the requirements placed on the power delivery network for a multilevel hierarchical system, due to aggressive voltage scaling and stringent limits on the chip-level voltage droop. This paper presents a methodology to obtain the minimal number of decoupling capacitors for a 4-level hierarchical system to meet the on-chip voltage droop constraints and to optimize the location of those decoupling capacitors to meet a user-specified target impedance. The number and location optimizations are performed using nature-based and Bayesian optimization algorithms along with the quantitative comparison of results.

Artificial Intelligence based advanced Signal Integrity prediction

Abstract: As the signaling speeds continue to increase, maintaining Signal Integrity (SI) for the complete customer design space is a huge challenge. These constraints, along with the limitations of traditional methods of design space inclusion and channel behavior prediction pose significant risk to system design. Specific focus is needed on design space utilization techniques used for factoring in platform variability. Interfaces like PCIe Gen5/Gen6/Gen4 etc. exhibit higher order behaviors that can’t be modelled by current prediction algorithm like Response Surface Method (RSM). This leads to inaccurate system behavior understanding and results in unreliable platform design recommendations. To minimize design risk and achieve highly reliable scaling of Platform Design Guide (PDG) solution, this paper discusses the implementation of an Artificial Intelligence (AI) based methodology to cover complete design space and predict higher order system behaviors with high accuracy. Current SI method involves RSM type Design of Experiments (DOE) creation and results prediction using second order RSM as shown in Fig. 2(a). It has limitations since RSM uses only three variable levels therefore doesn’t cover the entire design space. It can only model up to second order system behavior. These issues can be addressed using proposed AI based methodology shown in Fig. 2(b). These AI techniques have been encapsulated into an AI based tool called Fitpro which fully automates space filled DOE creation and SI results prediction. Fitpro significantly reduces manual interventions and positively impacts efficiency.

Development and Comparative Analysis of Delay Fault Models for Variants of High Speed CNT Interconnects at Submicron Technology

Abstract: Copper (Cu) has been meticulously used as an onchip connectivity material in VLSI chip design. This paper explores and investigates characteristics of carbon nanotubes (CNT) as high-speed VLSI interconnects. Delay faults are comparatively reduced in CNT interconnects with respect to Cu interconnects. It has been observed that variants of CNT interconnects experiences delay fault at quite later stage compared to Cu interconnects. SPICE based delay fault model has been considered here for fault analysis in on-chip interconnects. It has been depicted that SWCNT interconnect outperform compare to other CNT interconnects in terms of delay fault model analysis. The length of interconnect is varied from 1 μm to 100 μm for delay fault analysis at 16 nm technology node.

2x-Thru De-embedding Uncertainty for On-Package High-Speed Interconnects

Abstract: With the ever-increasing data rates, interconnect performance predictability becomes more and more challenging. Therefore, along with an accurate methodology, the quantification of measurement reproducibility and its impacts are essential in almost all aspects of high-speed interconnect validation. This paper investigates the reproducibility of S-parameter measurements before and after 2x-Thru de-embedding, and illustrates a multimetric correlation with uncertainty analysis.

A Dual-Band Compact Antenna Array with Scattering Suppression Capability in Low Band

Abstract: A new compact antenna with scattering suppression effects and operating in low band (LB) of 1.71 to 2.21 GHz is presented in this paper. Thanks to the effects, four very small-distance antennas operated in high band (HB, 3.3–3.6 GHz) are successfully interleaved with above one LB antenna, enabling our new dual-band compact antenna solutions..Simulated results shown that the antenna, with higher than 10dB of return loss in both band and 6.5dB/9.5dB of realized gain in LB/HB, has very promising for 5G applications.

Small Wireless Module Consisting of Two Highly Isolated MIMO PIFAs

Abstract: (Multi-input Multi-output)MIMO technology employs multiple antennas to send and receive signals. Using the MIMO technology, we obtain more data than that using traditional single antennas. Evaluating performance of dual transmitter, isolation in multiple antennas is an important parameter. The coupling effect in MIMO antennas will not only affect the characteristics of the antenna itself, but also the pattern, which will be compressed. In this paper, the PIFA = 1/4λ wavelength is used and realize the miniaturization of the antenna body and the PIFA architecture is beneficial to current distribution, that direct improve the isolation to − 20dB. In this paper, we propose two wide band and high isolation small PIFAs printed on 5G module to cover the 5 GHz ISM band. The module dimensions is 40 mm × 30 mm, antenna area dimensions is 7 mm × 30 mm and has a 100% available wide bandwidth in the range of 5.5 GHz to 6.5 GHz

Latency Insertion Method for FinFET DC Operating Point Simulation Based on BSIM-CMG

Abstract: As the scaling of planar MOSFETs progresses, various short-channel effects become prominent. The 3-dimensional FinFET was invented to avoid these short-channel effects. Transistor-level simulation with FinFETs is traditionally conducted by SPICE which has super-linear computational complexity. We propose a new method for FinFET DC operating point simulation through the use of the latency insertion method (LIM) which exhibits linear computational complexity. The algorithm incorporates the BSIM-CMG industry-standard compact model. The method is tested on 10 nm and 20 nm FinFETs, and the results are compared with commercial simulators.

Deep Reinforcement Learning-based Decoupling Capacitor Optimization Method for Multi-Power Domain considering Transfer Noise in 3D-ICs

Abstract: In this paper, we propose a deep reinforcement learning (DRL)-based multi-power distribution network (PDN) decoupling capacitor design optimization method considering transfer noise in 3D-ICs. The transfer noise from multi-PDN with vertical structures could cause system failure, the entire simultaneous switching noise (SSN) with the combined transfer noise should be considered. To address the multi-PDN problem, we use reinforcement learning suitable for solving complex optimization problems. The input dataset and Markov decision process (MDP) were designed to optimize various multi-PDN cases. The 5x4 size of two PDNs with a vertically stacked structure was used for verification. The proposed method successfully optimizes the decoupling capacitors of multi-PDN. In addition, the proposed method was compared to genetic algorithm (GA), the proposed method perfomed better optimization and reduced the time by about 99% compared to GA to 0.08 seconds.

Efficient Discharge Waveform Distribution Measurement Using Active Machine Learning

Abstract: Near-field scanning (NFS) is a promising method to capture the current propagation in an electronic system through an automated scanning system. This article presents a novel and efficient measurement method for discharge waveform distribution based on active machine learning using NFS. Implicitly, the query-by-committee (QBC) active learning method is adopted to select scanning points with high uncertainty. The proposed approach is computationally efficient in real-time NFS, demonstrates higher reconstruction accuracy than random sampling using the same amount of sparse samples, and is much more efficient than full scanning.

Hybrid Copper-Graphene Package Interconnects for Channel Loss Improvement in High-Speed Serial Interfaces

Abstract: Data rates in high-speed interfaces like upcoming PCIe Gen6, SERDES, Ethernet are continuously increasing, and the design specifications are becoming more stringent to ensure required performance. Any small variation in the specifications will have significant impact on signal integrity and affect the performance. This means that the total insertion loss, ISI, non-ISI jitter in the entire interconnect should be improved.IC package plays a key role in signal integrity of the high-speed signal and there is a need to have low loss channel. Standards like PCIe have a loss requirement of 4 dB combining silicon and package, in case of non-root complex. Recent developments suggest new design trends for multi-chiplets in a single package with increasing package sizes, which can make it extremely difficult to predict insertion loss specifications. Conductivity, dielectric properties, and loss tangent drives the overall loss per unit length and the current low-loss materials have insertion loss of around 1 dB per 10 mm. While many advances have been reported in the literature, scope for improvement exists and conventional approaches of lowering DF of dielectric material or reducing the surface roughness of Copper have helped but are not adequate for the demands of high-speed interconnects. This paper proposes a novel approach by using hybrid Copper-Graphene package interconnects, which helps in reducing signal losses and improves the overall performance of the system.

A Novel High Capacitance Ratio RF MEMS Switch with Low Pull-in Voltage

Abstract: An RF MEMS capacitive switch, which has a high capacitance ratio and low pull-in voltage, is designed and analyzed in this paper. The switch can change the switch’s up and down state (on and off state) capacitance by adding an H-shaped floating metal layer on the dielectric layer, which dramatically improves the capacitance ratio of the switch without changing the switch’s material and structure. The switch’s pull-in voltage is reduced by bending the spring beam to lower the switch spring coefficient. Finally, through theoretical analysis and finite element simulation, the obtained pull-in voltage is 4.7 V. When the switch is working at 33 GHz, the isolation is −60 dB, the insertion loss is −0.42 dB, and the capacitance ratio is 301. The switch shows good performance.

Training Set Optimization with Uncertainty Quantification for Machine Learning Models of Electromagnetic Structures

Abstract: Neural Networks surrogate modeling for EM simulations saves computational and design time. Introducing uncertainty estimates into deterministic prediction models provides insight into the reliability and confidence of the model. However, gathering training data to train models is a very time-consuming and resource-consuming task. In this paper, we introduce a method to harness useful insights from confidence bounds to reduce the training set size required to train a model with reasonable accuracy and latency. Using a high-speed differential via structure, we show that the training samples required are 35% less with a slight trade-off in accuracy using the proposed method.

Design and Analysis of Power Integrity of DDR5 Dual In-Line Memory Modules

Abstract: In today’s high speed design space, speed is the main factor determining the performance of the product. Dual In-line memory modules (DIMM) designs for DDR5 are packed with many high-speed DRAMs with signal speeds high enough that stack-up of the printed circuit board (PCB) play a critical role in the overall DIMM performance. At speeds of 6400 Mbps, power integrity becomes as important as signal integrity. On a first order approximation, power integrity basically involves PCB stack-up and decoupling capacitors design. This paper covers significance of power distribution network (PDN) symmetry in a symmetric stack-up for two-sided component mounted PCBs like DIMM modules running at multi-Gbps speeds.

Acceleration of Vector Fitting by Reusing the Householder Reflectors in Multiple QR Factorization

Abstract: The classic method of accelerating vector fitting (VF) for a multiport network is to do several small QR factorizations to extract the R22 matrices before solving the least-square system. In the literature and some open-source VF implementations, each QR factorization is performed separately. Taking a closer look at the theory, however, we can see that the first block of the matrices being factorized are the same, which means the computational cost can be reduced if the factorization of this part is skipped. To achieve this goal, however, we cannot simply call the high-level QR functions offered in many computational packages; instead, we must go down to the bottom level of QR factorization and reuse the Householder reflectors directly. In this paper, the theory and implementation of this idea is presented in detail. The theoretic flop reduction is roughly 25%, while in actual tests the time reduction may reach 60%.

Channel Impedance Optimization For 100 Gbps High-Speed Networking Interfaces

Abstract: High-speed designs today have multiple high-speed interfaces, and these interfaces have different impedance requirements in the same system. For example: PCIe interface is designed for 85 ohms whereas Gigabit ethernet is designed for 100 ohms. Sometimes due to stack-up cross-sectional restrictions and fixed dielectric constant of the material, it is not easy to meet all characteristic impedance requirements in the design. Design trade-off needs to be performed to analyze which interface is sensitive to impedance variations. With signal speeds going above 100 Gbps, pulse amplitude modulation-4 (PAM4) has become more common and PAM4 signaling is more sensitive to impedance variations due to low signal-to-noise ratio (SNR).In this paper, the impact of channel impedance on 100 Gbps ethernet (802.3ck) interface is analyzed using time-domain and frequency domain analysis. Channel operating margin (COM) analysis is performed for various channel impedances on an 802.3ck-CR topology. It Is found that huge impedance mismatch between the trace breakout and channel impacts channel performance adversely.

A High-Sensitive Resonant Cavity for Measuring Concentration of Aqueous Solutions

Abstract: This paper presents a small size cylinder resonant cavity with metal posts embedded for detecting the concentration of aqueous solutions. Compared with a regular cylinder cavity operating in the same mode TM011, the electrical field is more focused on near the tube containing materials under test (MUT), hence, the sensitivity of the cavity is enhanced. Three types of solutions are simulated including glucose, NaCl, and ethanol, varying in concentration from 0 to 5%, the results show that sensitivity is generally improved compared to the regular cavity, with glucose/water from 14 MHz/1% to 46.5 MHz/1%, NaCl/water from 36 MHz/1% to 162.5 MHz/1%, and ethanol/water from 20 MHz/1% to 66 MHz/1%.

A Compensation Amplifier with Automatic Zeroing and Stable Chopping

Abstract: This paper proposes a compensation (or error) amplifier with rail-to-rail input and output ranges. The amplifier combines automatic zero adjustment technology and stable chopper to suppress its offset related ripple. Two rail-to-rail input fully differential operational amplifiers in parallel can realize that when one operational amplifier is in the amplification state, the other operational amplifier is in the feedback state. The two amplifiers are interleaved for common mode feedback adjustment, so that the whole compensation amplifier has different states: common mode feedback, offset sampling and amplification. An eight-frequency clock module is integrated in the compensation (or error) amplifier to supply power to each enable end of the amplifier. Finally, it outputs through the third amplifier, which makes the operational amplifier have the advantages of large bandwidth and high accuracy compared with the traditional operational amplifier.