International Symposium on System-on-Chip 

About: International Symposium on System-on-Chip is an academic conference. The conference publishes majorly in the area(s): System on a chip & CMOS. Over the lifetime, 691 publications have been published by the conference receiving 4863 citations.

Spidergon: a novel on-chip communication network

Abstract: Summary form only given The SoC (System on Chip) design demands for novel architectural and circuital solutions to cope with the global wires issue, pushing the on-chip communication as a crucial and precious resource In the context of the communication centric paradigm and according to a layered based design, it is foreseen that current on-chip shared bus will be, at least partially, replaced by a micronetwork interconnection implementing a flexible packet-based communication (A Jantsch and H Tenhunen, "Networks on Chip", Kluwer Academic Publishers, 2003) We state that the availability of an efficient on-chip communication platform is one of the most important enabling factors for the development of efficient and cost effective multi processor SoC in the near and long-term future This summary presents the low cost, high performance on-chip communication network, called Spidergon, developed by the AST (Advanced System Technology) of STMicroelectronics as the possible evolution of STBus technology

Energy Model of Networks-on-Chip and a Bus

Abstract: A network-on-chip (NoC) is an energy-efficient on-chip communication architecture for multi-processor system-on-chip (MPSoC) architectures. In earlier papers we proposed two network-on-chip architectures based on packet-switching and circuit-switching. In this paper we derive an energy model for both NoC architectures to predict their energy consumption per transported bit. Both architectures are also compared with a traditional bus architecture. The energy model is primarily needed to find a near optimal run-time mapping (from an energy point of view) of inter-process communication to NoC links.

Congestion-aware task mapping in heterogeneous MPSoCs

Abstract: Multiprocessors systems-on-chip (MPSoCs) are a trend in VLSI design, since they minimize the design crisis represented by the gap between the silicon technology and the actual SoC design capacity. MPSoCs may employ NoCs to integrate several programmable processors, specialized memories, and other specific IPs in a scalable way. Besides communication infrastructure, another important issue in MPSoCs is task mapping. Dynamic task mapping is needed, since the number of tasks running in the MPSoC may exceed the available resources. Most works in literature present static mapping solutions, not appropriate for this scenario. This paper investigates the performance of mapping algorithms in NoC-based heterogeneous MPSoCs, targeting NoC congestion minimization. The use of the proposed congestion-aware heuristics reduces the NoC channel load, congestion, and packet latency.

Highly scalable network on chip for reconfigurable systems

Abstract: An efficient methodology for building the billion-transistors systems on chip of tomorrow is a necessity. Networks on chip promise to be the solution for the numerous technological, economical and productivity problems. We believe that different types of networks are required for each application domains. Our approach therefore is to have a very flexible network design, highly scalable, that allows to easily accommodate the various needs. This paper presents the design of our network on chip, which is part of the platform we are developing for reconfigurable systems. The present design allows us to instantiate arbitrary network topologies, has a low latency and high throughput.

Fast Multi-Dimension Multi-Choice Knapsack Heuristic for MP-SoC Run-Time Management

Abstract: Since the application complexity is growing and applications can be dynamically activated, the major challenge for heterogeneous multi-processor platforms is to select at run time an energy-efficient mapping of these applications. Taking into account that many different possible implementations per application can be available, and that the selection must meet the application deadlines under the available platform resources, this optimization problem can be modeled as a Multi-dimension Multi-choice Knapsack Problem (MMKP), being NP-hard. Not only algorithms for exact solution, but also state-of-the-art heuristics for real-time systems, are still too slow for run-time management of multi-procesor platforms. This paper provides a new greedy heuristic for finding near-optimal solutions of the MMKP, being fast enough for the considered environment. The main contribution of this heuristic is: (1) the derivation of the Pareto sets from the initial MMKP to reduce the search space, (2) the sorting of all Pareto points together in a single two-dimension search space, where (3) a fast greedy algorithm solves the MMKP. Experiments show that our heuristic finds solutions close to the ones obtained by the fastest state-of-the-art heuristics (within 0% to 0.4% of the solution value), in just a fraction of the execution time (more than 97.5% gain on a StrongARM processor) and can run in less than 1ms for multi-processor problem sizes.