Showing papers by "Amkor Technology published in 2016"

Substrate Trace Modeling for Package Warpage Simulation

Abstract: Accurately predicting warpage using finite element simulation helps accelerate decision-making in the early product development phase. With the ongoing trend of thinning the overall thickness of the microelectronics package as well as its substrate, copper with high modulus and coefficient of thermal expansion becomes more prominent compared to the rest of the non-metallic material. Package warpage simulation may need to consider the copper trace pattern. Due to the complexity of the copper trace, simulation with high fidelity can be extremely expensive. This paper examines the substrate copper structural features and their impact to the mechanical behaviors of real substrates. Finite element analysis simulations compared three copper trace modeling approaches at different packaging levels of bare substrate, bare die package, and overmold package. Warpage measurements of test vehicle packages using the exact copper trace patterns as simulations confirmed the analyses. A practical and efficient approach for package simulation is identified.

Development of Next Generation Flip Chip Interconnection Technology Using Homogenized Laser-Assisted Bonding

Abstract: Conventional flip chip technologies such as the mass reflow (MR) process and the thermal compression bonding (TCB) process are commonly used technologies in the micro assembly field. However, there is a continuous need for next generation interconnection technology to achieve a low form factor with increasing die and substrate complexities. Moreover, very thin 3D integrated packages and 2.5D packages with thin interposer die promise advanced interconnection technologies for mobile and wearable applications. With this point of view, the most important factor in interconnection is optimal thermal energy control for soldering. However, a conventional MR process cannot provide any selectivity and controlled thermal energy transferring with the traditional convection reflow. Its high thermal budget makes warpage an issue, aside from other side effects. To overcome the MR process problems, recent researches and industries have focused on developing a TCB process with non-conductive paste (NCP) or non-conductive film (NCF) due to TCB's unique advantages of low mechanical and thermal stress. However, the productivity of the TCB process is not comparably to the conventional process. Laser-assisted bonding (LAB) with beam homogenizer is considered to be the next generation interconnection technology due to its excellent thermal selectivity, extremely fast ramping up speed with purely controlled wavelength. This LAB process offers a very stable interconnection quality as well as robust functional and reliability result. Interestingly, it also achieves excellent results with thin coreless substrate due to its selective heating area availability. This paper will discuss the laser heating mechanism, multi-chip & component bonding availability and advantage of LAB from an assembly industrial perspective.

Fingerprint sensor and manufacturing method thereof

Abstract: A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise a sensing area on a bottom side of a die without top side electrodes that senses fingerprints from the top side, and/or that comprise a sensor die directly electrically connected to conductive elements of a plate through which fingerprints are sensed.

Wafer Level Multi-chip Gang Bonding Using TCNCF

Abstract: High throughput interconnection technology has been achieved using a multi-chip gang bonding process with an advanced chip on wafer (CoW) test vehicle (TV). The TV had 30 µm of fine-pitch copper pillar (CuP) and the bonding test was performed using non-conductive film (NCF). Therefore, all the steps including NCF lamination, wafer back-grinding and sawing, and thermo-compression bonding (TCB) were accomplished at the wafer level. Firstly, a layer of non-conductive film (NCF) was laminated on top of the wafer prior to back-grind and saw processes. Secondly, eight multi chips of 6x8 mm2 and 4x8 mm2 having 200 µm thickness were attached and aligned serially on the interposer wafer. For micro-bump interconnection, parallel bonding for the eight chips was applied for a few seconds after the serial chip attach process. Visual inspection and measurement confirmed the lateral fillet coverage was less than 110 µm without resin bleed-out and creeping. Destructive and non-destructive analyses were performed to examine solder joint formation & void inspection. Finally, reliability test was performed to confirm stability of the bonding process in a moisture resistance test (MRT) of L2Aa (60'C/60%RH, 120hrs) and L3 (30'C/60RH%, 192hrs) and temperature cycle (T/C) B 1000x. Electrical resistance was measured by probing for micro-bumps that are daisy-chained together. The resistance showed negligible change in upper and lower limit and no electrical failures or delamination occurred after reliability conditioning.

Semiconductor package using a coreless signal distribution structure

Abstract: A semiconductor package using a coreless signal distribution structure (CSDS) is disclosed and may include a CSDS comprising at least one dielectric layer, at least one conductive layer, a first surface, and a second surface opposite to the first surface. The semiconductor package may also include a first semiconductor die having a first bond pad on a first die surface, where the first semiconductor die is bonded to the first surface of the CSDS via the first bond pad, and a second semiconductor die having a second bond pad on a second die surface, where the second semiconductor die is bonded to the second surface of the CSDS via the second bond pad. The semiconductor package may further include a metal post electrically coupled to the first surface of the CSDS, and a first encapsulant material encapsulating side surfaces and a surface opposite the first die surface of the first semiconductor die, the metal post, and a portion of the first surface of the CSDS.

Method for fabricating semiconductor package and semiconductor package using the same

Abstract: Provided are a method for fabricating a semiconductor package and a semiconductor package using the same, which can simplify a fabricating process of the semiconductor package by forming a lead frame on which a semiconductor die can be mounted without a separate grinding process, and can improve product reliability by preventing warpage from occurring during a grinding process. In one embodiment, the method for fabricating a semiconductor package includes forming a frame on a carrier, forming a first pattern layer on the frame, first encapsulating the frame and the first pattern layer using a first encapsulant, forming conductive vias electrically connected to the first pattern layer while passing through the first encapsulant, forming a second pattern layer electrically connected to the conductive vias on the first encapsulant, forming a first solder mask formed on the first encapsulant and exposing a portion of the second pattern layer to the outside, removing the frame by an etching process and etching a portion of the first pattern layer, and attaching a semiconductor die to the first pattern layer.

System and method for laser assisted bonding of semiconductor die

Abstract: A system and method for laser assisted bonding of semiconductor die. As non-limiting examples, various aspects of this disclosure provide systems and methods that enhance or control laser irradiation of a semiconductor die, for example spatially and/or temporally, to improve bonding of the semiconductor die to a substrate.

Land structure for semiconductor package and method therefor

Abstract: In one embodiment, a method for forming a package substrate includes selectively removing portions of a lead frame to form cavities and filling the cavities with a resin layer to define an adhesion pad and a land structure. Top portions of the lead frame are selectively removed to isolate the adhesion pad and the land structure from each other, to expose a top surface of the resin layer, and to form at least one land having a part with a relatively greater size than the size of a respective lower part.

Electronic package structure

Abstract: An electronic package includes a lead frame structure having one or more structural features configured to improve board level reliability. In one embodiment, the structural feature comprises lead frame protrusions extending outward from the electronic package, which are configured to laterally engage solder structures used to attach the electronic package to a next level of assembly. In another embodiment, conductive bumps are attached to exposed portions of the lead frame in advance of next level assembly processes. In a further embodiment, the lead frame comprises laterally separated contact points for attaching an electron die and for attaching the electronic package to a next level of assembly.

Shielded electronic component package

Abstract: An electronic component package includes a substrate and an electronic component mounted to the substrate, the electronic component including a bond pad. A first antenna terminal is electrically connected to the bond pad, the first antenna terminal being electrically connected to a second antenna terminal of the substrate. A package body encloses the electronic component, the package body having a principal surface. An antenna is formed on the principal surface by applying an electrically conductive coating. An embedded interconnect extends through the package body between the substrate and the principal surface and electrically connects the second antenna terminal to the antenna. Applying an electrically conductive coating to form the antenna is relatively simple thus minimizing the overall package manufacturing cost. Further, the antenna is relatively thin thus minimizing the overall package size.

Semiconductor package having routable encapsulated conductive substrate and method

Abstract: A packaged semiconductor device includes a routable molded lead frame structure with a surface finish layer In one embodiment, the routable molded lead frame structure includes a first laminated layer including the surface finish layer, vias connected to the surface finish layer, and a first resin layer covering the vias leaving the top surface of the surface finish layer exposed A second laminated layer includes second conductive patterns connected to the vias, bump pads connected to the second conductive patterns, and a second resin layer covering one side of the first resin layer, the second conductive patterns and the bump pads A semiconductor die is electrically connected to the surface finish layer and an encapsulant covers the semiconductor die and another side of the first resin layer The surface finish layer provides a customizable and improved bonding structure for connecting the semiconductor die to the routable molded lead frame structure

Semiconductor product with interlocking metal-to-metal bonds and method for manufacturing thereof

Abstract: A structure and method for performing metal-to-metal bonding in an electrical device. For example and without limitation, various aspects of this disclosure provide a structure and method that utilize an interlocking structure configured to enhance metal-to-metal bonding.

Semiconductor package and manufacturing method thereof

Abstract: Thermal resistance is reduced from an element surface of a semiconductor chip to the rear surface of a semiconductor package Split patterning of a metal is easily carried out, stress produced by a thermal expansion coefficient between silicon and metal is significantly reduced and environment reliability is improved Low cost is realized by manufacturing a semiconductor package without using a TIM material A semiconductor package is provided including a semiconductor chip including a first surface and a second surface opposed to the first surface and covered with a resin, an electrode being arranged over the first surface, a first wiring connected to the first surface directly or via a first opening arranged in the resin, and a second wiring connected to the second surface via a second opening arranged in the resin

Semiconductor device with an electromagnetic interference (emi) shield

Abstract: A method for forming a semiconductor device with an electromagnetic interference shield is disclosed and may include coupling a semiconductor die to a first surface of a substrate, encapsulating the semiconductor die and portions of the substrate using an encapsulant, placing the encapsulated substrate and semiconductor die on an adhesive tape, and forming an electromagnetic interference (EMI) shield layer on the encapsulant, on side surfaces of the substrate, and on portions of the adhesive tape adjacent to the encapsulated substrate and semiconductor die. The adhesive tape may be peeled away from the encapsulated substrate and semiconductor die, thereby leaving portions of the EMI shield layer on the encapsulant and on the side surfaces of the substrate with other portions of the EMI shield layer remaining on portions of the adhesive tape. Contacts may be formed on a second surface of the substrate opposite to the first surface of the substrate.

Semiconductor package including premold and method of manufacturing the same

Abstract: A semiconductor package including a premold which is used to define support structure for a semiconductor die which is mounted to the premold by a layer of suitable adhesive. Embedded within the premold are lands which each include oppose upper and lower surfaces exposed in respective ones of upper and lower surfaces define by the premold. The semiconductor die, which is attached to the upper surface of the premold by the adhesive layer, is electrically connected to the exposed upper surfaces of the lands through the use of conductive wires. The semiconductor die, conductive wires, and the upper surface of the premold are covered or encapsulated by a package body. The package body does not cover any portion of the lower surface of the premold, thus allowing the exposed lower surfaces of the lands to be placed into electrical connection or communication with an underlying substrate such as a PCB or motherboard.

Finger print sensor and manufacturing method thereof

Abstract: A fingerprint sensor device and a method of making a fingerprint sensor device. As non-limiting examples, various aspects of this disclosure provide various fingerprint sensor devices, and methods of manufacturing thereof, that comprise a substrate comprising a dielectric layer and a wiring pattern embedded in and exposed from the dielectric layer.

Semiconductor device having conductive wire with increased attachment angle and method

Abstract: A semiconductor device includes a shielding wire formed across a semiconductor die and an auxiliary wire supporting the shielding wire, thereby reducing the size of a package while shielding the electromagnetic interference generated from the semiconductor die. In one embodiment, the semiconductor device includes a substrate having at least one circuit device mounted thereon, a semiconductor die spaced apart from the circuit device and mounted on the substrate, a shielding wire spaced apart from the semiconductor die and formed across the semiconductor die, and an auxiliary wire supporting the shielding wire under the shielding wire and formed to be perpendicular to the shielding wire. In another embodiment, a bump structure is used to support the shielding wire. In a further embodiment, an auxiliary wire includes a bump structure portion and wire portion and both the bump structure portion and the wire portion are used to support the shielding wire.

High-speed flip chip package Co-Design with Optimization of anti-pad size variations on metal plane layout

Abstract: Co-Design with Optimization of Physical Plane Layout in FCBGA substrate is imperative for the high-speed chips to perform the best performance. It was found that ground metal plane void (anti-pad) under ball pads and core via pads had correlation with insertion and return loss. We focused on optimizing metal and trace layout of the high-speed signal net, also known as SerDes (Serializer-Deserializer) that operates frequency in Gigahertz Transceiver. It exhibits that the quality of critical signal does not only depend on the surface trace, but it also very depends on the ground metal plane layout with metal void (anti-pad) size variation against via which the path of trace-to-via discontinuities has been ignored in the field. This study shows the characteristic impedance of via can be managed by changing the capacitance of via path with modified ground metal clearance to via, which will be closed to the characteristic impedance of the surface trace for reducing return loss. So this paper proposes that simulation-based Co-Design can be provided optimized metal void (anti-pad) design for the better electrical performance of the critical signals. By applying the proposed co-design, its design rule and device in FCBGA can be optimized in the design phase.

Electronic device package and fabricating method thereof

Abstract: Various aspects of the present disclosure provide a semiconductor device, for example comprising a finger print sensor, and a method for manufacturing thereof. Various aspects of the present disclosure may, for example, provide an ultra-slim finger print sensor having a thickness of 500 μm or less that does not include a separate printed circuit board (PCB), and a method for manufacturing thereof.

Electronic device with a plurality of redistribution structures having different respective sizes

Abstract: A semiconductor device with enhanced interposer quality, and method of manufacturing thereof. For example and without limitation, various aspects of the present disclosure provide an interposer die that comprises a first signal distribution structure comprising at least a first dielectric layer and a first conductive layer, wherein the signal distribution structure is protected at lateral edges by a protective layer. Also for example, various aspects of the present disclosure provide a method of manufacturing a semiconductor device comprising such an interposer die.

Semiconductor package with clip alignment notch

Abstract: An electronic component includes a leadframe and a first semiconductor die. The leadframe includes a leadframe top side, a leadframe bottom side opposite the leadframe top side, and a top notch at the leadframe top side. The top notch includes a top notch base located between the leadframe top side and the leadframe bottom side, and defining a notch length of the top notch, and can also include a top notch first sidewall extended, along the notch length, from the leadframe top side to the top notch base. The first semiconductor die can include a die top side a die bottom side opposite the die top side and mounted onto the leadframe top side, and a die perimeter. The top notch can be located outside the die perimeter. Other examples and related methods are also disclosed.

Capacitor of semiconductor integrated circuit and method for manufacturing the same

Abstract: Provided are a capacitor of a semiconductor integrated circuit and a method for manufacturing the same, for example a metal-insulator-metal (MIM) type capacitor of a semiconductor integrated circuit, which is capable of improving adhesive force between an electrode layer and a dielectric layer of a capacitor, and a method for manufacturing the same. For example, the present disclosure provides a capacitor for a semiconductor integrated circuit having a new structure, which is capable of preventing a delamination phenomenon on an interface between a lower electrode layer and a dielectric layer by further forming a buffer layer, which is capable of decreasing or compensating for a difference in a coefficient of thermal expansion, between a metal electrode layer and a dielectric layer, particularly, between the lower electrode layer and the dielectric layer, and a method for manufacturing the same.

Method for fabricating semiconductor package having a multi-layer molded conductive substrate and structure

Abstract: In one embodiment, a method for fabricating a semiconductor package includes providing a multi-layer molded conductive structure. The multi-layer molded conductive structure includes a first conductive structure disposed on a surface of a carrier and a first encapsulant covering at least portions of the first conductive structure while other portions are exposed in the first encapsulant. A second conductive structure is disposed on the first encapsulant and electrically connected to the first conductive structure. A second encapsulant covers a first portion of the second conductive structure while a second portion of the second conductive structure is exposed to the outside, and a third portion of the second conductive structure is exposed in a receiving space disposed in the second encapsulant. The method includes electrically connecting a semiconductor die to the second conductive structure and in some embodiments removing the carrier.

An Innovative Package EMC Solution Using a Highly Cost-Effective Sputtered Conformal Shield

Abstract: High-speed digital and wireless devices radiate undesired electromagnetic noises that affect the normal operation of other devices causing electromagnetic interference (EMI) problems. Printed circuit board (PCB) and system-level shielding may alleviate inter-system EMI between the PCB board and the outside environment, but does not prevent intra-system EMI within the shielding enclosure. Package and System in Package (SiP) level shielding is often used to minimize intra-system EMI issues. An external metal lid is traditionally employed to prevent noise emission from a device, but the cost and size of this technique makes it unattractive for modern electronics. Conformal shielding is gaining momentum due to its size and height advantages. However, high cost and complexity of the sprayed coating shield prevents it from being used for a wide range of low cost commercial applications. In this paper, an innovative shielding technology with sputtered metal conformal shield is investigated using a specially desi...

Improved router & server OPEX, acoustics and leakage power through advancements in ASIC / CPU design

Abstract: Increasing thermal demands for high-end server CPUs and Router/Switch ASICs require increased performance for the air-cooled system thermal design in order to meet increasing industry needs. Improving the CPU/ASIC package thermal performance is one of the critical areas for improving multiple system level thermal design issues. This includes (a) increasing the maximum CPU/ASIC power; (b) reducing the leakage power dissipation and associated OPEX through attaining a lower junction temperature; (c) lowering OPEX by being able to reduce air flow requirements and associated power required for the air movers; and (d) reducing the server OSHA sound pressure level, along with reducing the router/switch NEBS acoustic sound power level due to realizing a lower air flow requirement.

A semiconductor package having an etched groove for an embedded device formed on bottom surface of a support substrate and a method for fabricating the same

Abstract: A semiconductor device with etched grooves for embedded devices is disclosed and may, for example, include a substrate comprising a top surface and a bottom surface, a groove extending into the substrate from the bottom surface, and a redistribution structure in the substrate between the top surface and the bottom surface of the substrate. A semiconductor die may, for example, be coupled to the top surface of the substrate. An electronic device may, for example, be at least partially within the groove and electrically coupled to the redistribution structure. A conductive pad may, for example, be on the bottom surface of the substrate. A conductive bump may, for example, be on the conductive pad. The electronic device in the groove may, for example, extend beyond the bottom surface of the substrate a distance that is less than a height of the conductive bump from the bottom surface of the substrate. An encapsulant may, for example, encapsulate the semiconductor die and the top surface of the substrate. The electronic device may, for example, comprise a capacitor.

System level IC packaging - Integration of Key Technologies: TSVs, Interposers, and Advanced IC Packaging

Abstract: New system level IC package integration requires a flexible assembly portfolio. A review of current wafer scale processing and assembly solutions and new development directions is warranted. 2.5D TSV System level IC packaging is not new, but the performance levels that are being attained today with memory stacking, interposers, advanced silicon nodes and advanced packaging are new and are unparalleled. Several key technologies have come together to create this bold shift to higher performance. The Thru-Silicon Via (TSV) technology has been foremost, whether in the interposer, memory or logic devices, the importance of the this electrical pass through connection in silicon cannot be overstated. To commercialize the TSV package constructions, IC packaging technology had to be developed to permit its use. This included TSV reveal on TSV-bearing interposers, new ways of controlling warpage due to the presence of large x-y interposers, new functional IC bumping technologies and attachment methods. This portfol...

Improving Copper Pillar Interconnection on Embedded Trace Substrates

Abstract: In the push for thinner packages for applicationprocessors, baseband processors, and other devices, EmbeddedTrace Substrates (ETS) have found quick adoption in themicroelectronics packaging industry. ETS offer several benefitsover conventional cored substrates, such as dielectric layerthickness reduction, layer count reduction, and lowermanufacturing costs. In parallel, copper pillar interconnectshave become a standard for devices that fall into the FlipChip/Chip Scale Package (fcCSP) envelope. Copper pillartechnology provides long-term reliability, high bumping yields, and very fine pitch interconnects, all of which have becomemandatory attributes for advanced devices. As a result, copperpillar technology with ETS is now a popular choice for low-cost, robust solutions to many of the most demanding deviceapplications. While ETS have many benefits, they suffer riskswhich cored Protruded Trace Substrates do not, namely, areduced trace surface area for first-level interconnection and aninherent pad recess below the substrate surface. Both of thesecharacteristics increase the risk of non-wets occurring duringchip attach in device assembly. In order to take full advantage of the benefits of copperpillar technology and ETS, reliability risks must be reduced toa minimum. The present paper seeks to do so by identifying thekey geometric variables involved in the chip attach process ofcopper pillar bumps on ETS and developing a mathematicalmodel to understand how each variable plays a role in thewetting outcome of the chip attach process. The intended goal ofthis paper is to provide a useful tool to predict and ultimatelyreduce the risk of non-wets.

Semiconductor package using a polymer substrate

Abstract: A semiconductor package using a polymer substrate is disclosed and may include a polymer cavity structure comprising first metal traces, a micro-electro mechanical systems (MEMS) device and a semiconductor die bonded to a first surface within a cavity of the cavity structure, and a substrate coupled to the cavity structure and comprising second metal traces coupled to the first metal traces. The substrate may enclose the MEMS device and the semiconductor die. Ground traces may be on external surfaces of the polymer cavity structure. Ball lands may be on a surface of the substrate opposite to a surface with the second metal traces. The first metal traces may extend from the first surface of the polymer cavity structure up a sidewall of the cavity and to conductive patterns on a top surface of the polymer cavity structure.

Joint Healing Thermal Interface Material

Abstract: Today, thermal interface materials (TIM) are widely used between a processor die and an integrated heat-spreader (IHS) to provide a good thermal conduction path for heat transfer from the electronic package. As the current trend towards larger “die size designs” progresses, the performance and reliability of the TIM will be a greater challenge for thermal engineers. In these larger die size designs, the TIM will experience increased movement as a result of the coefficient of thermal expansion (CTE) mismatch between the die and the printed circuit board. Traditionally, indium and dispensable thermoset materials are utilized in this application. However, delamination of the TIM from one of the mating surfaces is becoming more common as these materials are unable to compensate for the increased movement. In addition, the increasing cost of indium metal is causing indium-based TIMs to become cost prohibitive while dispensable materials require frozen shipment and storage, creating logistics complicat...