Showing papers by "Amkor Technology published in 2019"

Ni Barrier Symmetry Effect on Electromigration Failure Mechanism of Cu/Sn–Ag Microbump

Abstract: Ni barrier symmetry effect on the electromigration (EM) failure mechanism of Cu/Sn–Ag microbump were systematically investigated by studying the intermetallic compound (IMC) growth characteristics at 150 °C with a current density of 1.5 × 105 A/cm2. In the symmetric Ni barrier structure, Cu diffusion to Sn–Ag solder was restricted by the Ni barrier at both interfaces and the Ni3Sn4 phase formed by the inter-diffusion between Ni and Sn atoms just after bonding, which was gradually transformed to (Ni,Cu)3Sn4 phase and later to (Cu,Ni)6Sn5 during current stressing with relatively slow resistance increase with time. By the way, in the asymmetric structure, extensive Cu6Sn5 phase grew by the inter-diffusion between Cu and Sn atoms due to there is no Ni barrier at the upper interface, which was rapidly transformed into only Cu6Sn5 and Cu3Sn IMCs during electron downward flow, with relatively fast resistance increase with time. Therefore, the symmetric Ni barrier structure is very effective in restricting extensive IMC reactions during EM of Cu-solder microbump structure.

Meander-Line Monopole Antenna With Compact Ground Plane for a Bluetooth System-in-Package

Abstract: In this letter, a packaged compact meander-line monopole antenna for Bluetooth communications, manufactured in low-density fan-out technology, is presented A combined size for the antenna and ground plane of $\bf 01\lambda _0\times 006\lambda _0\times 0008\lambda _0$ is obtained Such small antennas are usually designed considering their connection to an evaluation board with a large ground plane, which improves their gain and bandwidth, but in this letter, the antenna is designed so it can work standalone without any further connection to printed circuit boards The challenge of designing such a compact antenna is surpassed by performing a detailed modeling of the radiating meander-line element altogether with its finite ground plane, a tuning inductor, and an inductive coupling feed The antenna model is developed in Ansys HFSS using the finite element method, which is later validated experimentally Measurements of the return loss radiation pattern are carried out, and final results show a $-$ 6 dB bandwidth of approximately 110 MHz and a gain of $-$ 87 dBi, at 242 GHz

Semiconductor package having inspection structure and related methods

Abstract: An electronic device structure includes a leadframe with a die pad and a lead. A semiconductor die is mounted adjacent to the die pad. A clip having a clip tail section is attached to the lead. The clip further has a clip top section attached to the clip tail section, and the clip top section is attached to a die top side of the semiconductor die with a conductive material. The clip further has an opening disposed to extend through the clip top section. In one embodiment, after a reflow step the conductive material forms a conductive fillet at least partially covering sidewall surfaces of the opening, and has a height within the opening with respect to a bottom surface of the clip top section. The opening and the conductive fillet provide an improved approach to monitoring coverage of the conductive material between the clip top section and the die top side of the semiconductor die.

Effects of NCF and UBM Materials on Electromigration Reliabilities of Sn-Ag Microbumps for Advanced 3D Packaging

Abstract: The effect of non-conductive films (NCF) and under-bump metallization (UBM) materials on the electromigration (EM) failure mechanism of Sn-Ag microbumps was investigated under stress conditions at current densities ranging from 0.5~1.3 × 105 A/cm2 at 150°C. In the case of NCF microbumps, the EM failure mechanism were almost similar to that involving Cu/Ni/Sn-Ag microbumps with NCF and non-NCF. However, the NCF applications increased EM lifetime for the Cu/Ni/Sn-Ag microbumps. In the case of Ni and Cu UBM microbumps, the EM failure mechanism varied between Sn-Ag microbumps with Ni UBM and Cu UBM. No EM-induced failure was observed in Cu UBM microbump. However, EM-induced voids were found on the cathode side of the Al trace in the Ni UBM microbump. The three-dimensional (3-D) finite element method was used to simulate the current density and temperature distributions of the microbumps. The results showed that the Joule heating of the Ni UBM microbump was higher than that of the Cu UBM microbump. Thus, the increased Joule heating due to thicker Ni UBM resulted in a negative effect on the EM failure time. Therefore, the Cu UBM microbumps are expected to display enhanced EM resistance.

Embedded Wafer-Level Ball Grid Array (eWLB) Packaging Technology Platform

Abstract: Wafer‐level packaging (WLP) is one of the fastest‐growing packaging technologies on the market today. Fan‐out WLP (FO‐WLP) is the extension of WLP and provides higher input and output (I/O) capability. The version of FO‐WLP technology reviewed in this chapter is called embedded wafer‐level ball grid array (eWLB). Chip‐first technology can be distinguished in two different categories: die face‐down or die face‐up assembly approach during the construction of the molded wafer, also called the reconstituted wafer. The electrical performance of FO‐WLP generally is very good because of short, low resistance connections and very low parasitics. The chapter compares the warpage behavior and the electrical and thermal performance of different package platforms. The proof of electrical functionality is an important milestone for any package platform. Chip scale packages (CSP) are tested after singulation into discrete packages. FO‐WLP can also be tested after package singulation like CSP.

Low-Density Fan-Out Heterogeneous Integration of MEMS Tunable Capacitor and RF SOI Switch

Abstract: Using Low-Density Fan-Out (LDFO) packaging technology, a radio frequency (RF) microelectromechanical systems (MEMS) tunable capacitor array composed of electrostatically actuated beams on ...

Challenges and Approaches to Developing Automotive Grade 1/0 FCBGA Package Capability

Abstract: Automotive Grade 1 and 0 package requirements, defined by Automotive Electronics Council (AEC) Document AEC-100, require more severe temperature cycling and high temperature storage conditions to meet harsh automotive field requirements, such as a maximum 150°C device operating temperature, 15-year reliability and zero-defect quality level. Moreover, increased integration of device functionality to meet the new automotive requirements for in-vehicle networking, autonomous driving, infotainment and sensor integration are driving increases in die and package sizes. This paper provides an update on flip chip ball grid array (FCBGA) package development as quality and reliability requirements increase for larger and larger package form factors and approaches that should be taken to meet Grade 1/0 requirements. Package quality and wear-out failure modes and mechanisms experienced during extended reliability testing in Automotive Grade 2 and 3 package qualifications have identified thermomechanical stress and material degradation at high temperatures as key factors for focus in Grade 1/0 development. To achieve higher grade levels, key package substrate materials such as core, solder resist and build-up layers need to be evaluated as well as assembly materials such as underfills materials may need improvement. Mechanical simulation data of key material properties such as coefficient of thermal expansion (CTE), modulus of elasticity (E1) and glass transition temperature (Tg) of the substrate and assembly materials are used to provide guidance for the selection of substrate and assembly materials used in the design of experiments to meet Auto Grade 1 and 0 reliability requirements. Taguchi mechanical simulations results show that use of low CTE materials for the substrate core and build up material was beneficial in preventing SR cracking, UF cracking and bump cracking. Reliability stress results on design of experiments based on inputs from simulation resulted in developing a substrate and assembly material set that meets AEC100 solder resist (SR) Grade 1 and 0 package requirements on a 45-mm x 45-mm FCBGA.

Semiconductor device and method of manufacturing a semiconductor device

Abstract: An exemplary semiconductor device can comprise a die, a redistribution structure (RDS), an interconnect, a conductive strap, an encapsulant, and an EMI shield. The redistribution structure can comprise an RDS top surface coupled to the die bottom side. The interconnect can be coupled to the RDS bottom surface. The conductive strap can be coupled to the RDS, and can comprise a strap inner end coupled to the RDS bottom surface, and a strap outer end located lower than the RDS bottom surface. The encapsulant can encapsulate the conductive strap and the RDS bottom surface. The EMI shield can cover and contact the encapsulant sidewall and the strap outer end. Other examples and related methods are also disclosed herein.

Semiconductor device utilizing an adhesive to attach an upper package to a lower die

Abstract: An electronic device and a method of making an electronic device. As non-limiting examples, various aspects of this disclosure provide various methods of manufacturing electronic devices, and electronic devices manufactured thereby, that comprise utilizing an adhesive layer to attach an upper electronic package to a lower die and/or utilizing metal pillars for electrically connecting the upper electronic package to a lower substrate, wherein the metal pillars have a smaller height above the lower substrate than the lower die.

Development of FCBGA substrate with low Dk/Df material based on automotive reliability conditions

Abstract: With the recent emergence of AI and 5G, semiconductor packaging requires higher level of integration and ultra-fine technology. In the server and data center fields, trends are increasing number of I/O and package size. Advancements in autonomous vehicles and car infotainment are requiring higher level of packaging reliability. Areas requiring high-speed operation, fast response, and low delay such as server and autonomous are required to employ packaging materials with low dielectric constant (Dk) and low dielectric loss (Df). In this paper, study result for development of FCBGA substrate using low Df ABF material (GL102) is provided. The FCBGA substrate structure used in the experiment is 14 layer (6-2-6) and the dimension of the substrate is $47.5^{\ \ast}\ 47.5$ mm square.

Semiconductor device having stacked dies and stacked pillars and method of manufacturing thereof

Abstract: Various aspects of this disclosure provide a semiconductor device and a method of manufacturing a semiconductor device. As a non-limiting example, various aspects of this disclosure provide a semiconductor device comprising a stacked die structure and a method of manufacturing thereof.

SWIFT® Semiconductor Packaging Technology

Abstract: The continued scaling of transistor geometries for semiconductor devices has been placing an increased demand on the next‐level interconnect technologies. A new, innovative chip‐last high density fan‐out (HD‐FO) structure called Silicon Wafer Integrated Fan‐out Technology (SWIFT) packaging incorporates conventional fan‐out waferlevel packaging (FO‐WLP) processes with leading‐edge, thin film patterning techniques to bridge the gap between through‐silicon via technology and traditional FO‐WLP packages. For smartphones and wearable devices, 3D package‐on‐package (PoP) structures have become the standard for application processor (AP) and DRAM integration. SWIFT packaging is also capable of conformal shielding, which is increasingly requested for laminate‐based system in package (SiP) modules. In addition to the AP and SiP markets, SWIFT packaging has applications in the networking and high performance graphics segments. This chapter focuses on the comparison of the chip‐last HD‐FO technology process with both exposed‐die PoP and fan‐in PoP for signal integrity, power integrity, and impedance matching.

Electronic device with top side pin array and manufacturing method thereof

Abstract: An electronic device and a manufacturing method thereof. As non-limiting examples, various aspects of this disclosure provide an electronic device having a top side pin array, for example which may be utilized for three-dimensional stacking, and a method for manufacturing such an electronic device.

Heat sink attached to an electronic component in a packaged device

Abstract: A method for forming a packaged electronic device includes providing a substrate comprising a lead and a pad. The method includes attaching a thermally conductive structure to the pad and attaching an electronic component to one of the thermally conductive structure or the pad. The method includes electrically coupling the electronic component to the lead, and forming a package body that encapsulates the electronic component and at least portions of the lead, the pad, and the thermally conductive structure, wherein the package body has a first major surface and a second major surface opposite to the first major surface, and one of the first bottom surface of the thermally conductive structure or the bottom surface of the pad is exposed in the first major surface of the package body.

Electronic device with adaptive vertical interconnect and fabricating method thereof

Abstract: Electronic components and an electronic device comprising one or more of the electronic components, and a method of manufacturing the electronic components and an electronic device comprising one or more of the electronic components. As non-limiting examples, various aspects of this disclosure provide vertical interconnect components and various other vertical electronic components, and a method of manufacturing thereof, and an electronic device comprising one or more of the vertical interconnect components and various other vertical electronic components, and a method of manufacturing thereof.

Equipment and Process for eWLB

Abstract: During early fan‐out wafer‐level packaging (FO‐WLP), when Infineon was developing their embedded wafer‐level ball grid array technology, 200 mm physical vapor deposition (PVD) systems were used for development and initial production. The FO‐WLP PVD process flow involves the following stages: degas, pre‐clean, PVD adhesion layer deposition and copper seed layer deposition. After successful degas, the molded wafer needs to be pre‐cleaned in a plasma etch module. The pre‐clean process will involve an “over etch” to accommodate any cross‐wafer variation in the etch process. Epoxy‐molded wafers can be warped after curing, and the size and shape of the warpage hinge on the different size, density, and placement of the die. Multi‐wafer degas technology has emerged as a compelling solution to the degas throughput problem, enabling multiple wafers to be degassed in parallel before being individually transferred to subsequent process steps, without breaking vacuum.

Method of manufacturing an electronic device and electronic device manufactured thereby

Abstract: Various aspects of this disclosure provide a method of manufacturing an electronic device and an electronic device manufactured thereby. As a non-limiting example, various aspects of this disclosure provide a method of manufacturing an electronic device, and an electronic device manufactured thereby, that utilizes ink to form an intermetallic bond between respective conductive interconnection structures of a semiconductor die and a substrate.

Method of forming an electronic device structure having an electronic component with an on-edge orientation and related structures

Abstract: A method of forming an electronic device structure includes providing an electronic component having a first major surface, an opposing second major surface, a first edge surface, and an opposing second edge surface. A substrate having a substrate first major surface and an opposing substrate second major surface is provided. The second major surface of the first electronic component is placed proximate to the substrate first major surface and providing a conductive material adjacent the first edge surface of the first electronic component. The conductive material is exposed to an elevated temperature to reflow the conductive material to raise the first electronic component into an upright position such that the second edge surface is spaced further away from the substrate first major surface than the first edge surface. The method is suitable for providing electronic components, such as antenna, sensors, or optical devices in a vertical or on-edge.

Top port MEMS package and method

Abstract: A top port MEMS microphone package includes a substrate having a back volume expanding aperture therein. A MEMS microphone electronic component is mounted to the substrate directly above the back volume expanding aperture such that an aperture of the MEMS microphone electronic component is in fluid communication with the back volume expanding aperture. A lid having a lid cavity is mounted to the substrate. The back volume expanding aperture couples the aperture of the MEMS microphone electronic component to the lid cavity. By coupling the lid cavity to the aperture with the back volume expanding aperture, the resulting back volume is essentially the size of the entire top port MEMS microphone package. In this manner, the noise to signal ratio is minimized thus maximizing the sensitivity of the top port MEMS microphone package as well as the range of applications.

System and method for laser assisted bonding of an electronic device

Abstract: A system and method for laser assisted bonding of semiconductor die. As non-limiting examples, various aspects of this disclosure provide systems and methods that enhance or control laser irradiation of a semiconductor die, for example spatially and/or temporally, to improve bonding of the semiconductor die to a substrate.

Embedded ball land substrate, semiconductor package, and manufacturing methods

Abstract: A electronic device includes an embedded ball land substrate and a semiconductor die. The embedded ball land substrate includes a top surface, a bottom surface opposite the top surface, and one or more side surfaces adjacent the top surface and the bottom surface. The embedded ball land substrate further includes a mold layer on the bottom surface, contact pads on the top surface, and ball lands embedded in the mold layer and electrically connected to the contact pads. The semiconductor die includes a first surface, a second surface opposite the first surface, one or more side surfaces adjacent the first surface and the second surface, and attachment structures along the second surface. The semiconductor die is operatively coupled to the contact pads via the attachment structures.

Packaged electronic device having stepped conductive structure and related methods

Abstract: An electronic package includes a substrate having a conductive element. The conductive element includes a stepped portion disposed at an end of the conductive element. In one embodiment, the conductive element is a lead. In another embodiment, the conductive element is a die pad. The stepped portion includes a first groove extending inward from a lower surface of the first conductive element, and a second groove extending further inward from the first groove towards an upper surface of the conductive element. An electronic component is connected to the conductive element. In one embodiment, a clip is used to electrically connect the electronic component to the conductive element. An encapsulant encapsulates the electronic component and a portion of the substrate such that the stepped portion is exposed outside an exterior side surface of the encapsulant. The stepped portion is configured to improve the bonding strength of the electronic package when attached to a next level of assembly.