Showing papers by "Motorola published in 1980"

Stanby mode controller utilizing microprocessor

Abstract: Logic circuitry in a portable electronic device is combined with the microprocessor to reduce power consumption in the microprocessor and its associated memories during inactive periods of the device, with periodic sampling for inputs from peripherals or received data which would require active operation of the device.

Microprocessor with duplicate registers for processing interrupts

Abstract: A unique microprocessor for controlling portable and mobile cellular radiotelephones is architectured to process high speed supervisory signalling, while also minimizing power drain. The architecture of the microprocessor is organized around three buses, a data bus, a register bus and an address bus. Data signals are routed between the various blocks of the microprocessor by selectively interconnecting the three buses in response to control signals provided by ALU and control programmable logic arrays (PLA). The ALU and control PLA's decode program instructions loaded in instruction register (IR) to provide the appropriate control signals for executing each instruction. The microprocessor also includes three general purpose registers, an arithmetic logic unit (ALU) with two temporary registers and zero and carry flags, serial data bus circuitry including a format generator and two data registers, direct I/O data direction and data registers, a stack pointer counter, a twelve-bit program counter register, a temporary program counter register and associated incrementer, and a temporary address register. Because of the unique architecture of the microprocessor, all instructions can be executed in four or less clock cycles. Moreover, the program counter register, general purpose registers and zero and carry flags are duplicated, and, during interrupts, the microprocessor switches over to the duplicate program counter register, duplicate general purpose registers and duplicate zero and carry flags. As a result, interrupts are processed quickly and efficienty merely by switching back and forth between the program counter register, general purpose registers and zero and carry flags and their duplicates. Since instruction execution time is minimized, the microprocessor can be operated at slower speeds to conserve power drain, while maintaining the through-put necessary for accommodating high-speed, cellular type supervisory signalling. Thus, a microprocessor embodying the present invention can be advantageously utilized in any application where both low power consumption and fast data manipulation are required.

Acoustic transmitter and method to produce essentially longitudinal, acoustic waves

Abstract: A portable, electrohydraulic, acoustic transmitter releasably attaches to a solid medium such as a drill string to generate essentially longitudinal, acoustic signals in the medium. The signals are frequency modulated so that encoded messages may be transmitted between a surface and subsurface location to activate downhole equipment.

Microprocessor controlled radiotelephone transceiver

Abstract: An improved radiotelephone includes a unique microprocessor and peripheral devices for controlling the operation of portable or mobile radio transceivers in a cellular-type radiotelephone system. The microprocessor is coupled by a data interface unit and synchronization unit to the radio transceiver for transmitting and receiving Manchester-coded supervisory signalling having a 10 KHz bit rate. The microprocessor is also coupled by a unique self-clocking serial data bus and unique interface adapters to the radio transceiver for controlling the operating frequency, audio signals and transmitted RF signal thereof, to a keyboard for sampling the keys thereof, an off-hook switch and display for displaying telephone numbers, and to serial number and telephone number memories for accessing the stored serial and telephone numbers assigned to the radiotelephone. The microprocessor-controlled radiotelephone can be substantially adapted to operate a system selected from a wide variety of conventional and advanced radiotelephone systems by tailoring the microprocessor control program to meet the selected system specifications.

Dual mode transceiver antenna

Abstract: A dual mode antenna for a miniature radio transceiver includes a low profile loop antenna structure while mounted on a body and a high efficiency dipole antenna while held in the hand.

Analog to digital converter and method of calibrating same

Abstract: A single slope analog to digital converter uses a DAC (21) to trim the discharge current of a capacitor (10) during calibration thereof. A method of calibrating the analog to digital converter is provided which iterates required steps to obtain a correct current setting within a short period of time. The analog to digital converter discharges a capacitor (10) through a high impedance to obtain a linear discharge. The time to discharge the capacitor (10) appears in a counter and is indicative of the voltage across the capacitor (10) at the beginning of the discharge period once the analog to digital converter has been calibrated.

Conditional branch unit for microprogrammed data processor

Abstract: A data processor having a microprogrammed control store and including a conditional branch control unit for receiving selection bits output by the control store, selection bits from an instruction register, and conditional signals for generating a two-bit result which, when added to a base address, can specify one of two, three, or four branch destinations in the control store. The selection bits output by the control store determine whether the combination of conditional signals upon which the branch is dependent is selected by the control store or is selected directly by a bit field in the macroinstruction. Also, one of the selection bits output by the control store is used to select one of two possible output codes for the two-bit result associated with a particular branch destination. The latter feature allows for two conditional branch points in the control store to test for the same condition and to select the same destination when the tested condition is of one logic state while selecting different destinations when the tested condition is of the opposite logic state.

Method and apparatus for detecting a data signal including repeated data words

Abstract: A method and detector are described for detecting a data signal including at least three repeated data words each preceded by a Barker word. The detector includes a microcomputer that is responsive to interrupt and correlation programs for receiving and timewise correlating the repeated data words in the data signal. Upon detection of each Barker word, the microcomputer stores the following data word and measures the elapsed time interval between data words by measuring the time between detection of Barker words. The elapsed time interval between the previously and presently received data words is added to the stored time interval of all previously received data words. If at least three of the received data words have corresponding stored time intervals that are correlated with predetermined time interval ranges, a correlation indication signal is provided to indicate that valid data words have been received. The inventive method and detector may be advantageously utilized in mobile and portable stations of a radio communication system for receiving high speed data on a noisy voice channel.

Semaphore register including ownership bits

Abstract: A semaphore register for use in a peripheral controller includes a semaphore bit which when not set indicates the availability of a shared resource, an internal ownership bit which when set indicates ownership of the resource by a peripheral controller and an external ownership bit which when set indicates ownership of the resource by a host processor. If the semaphore is clear, upon receipt of a read signal from the peripheral controller, the semaphore bit and the internal ownership bit are set. Upon receipt of a read signal from the host processor, the semaphore bit and the external ownership bit are set. Arbitration logic includes means responsive to simultaneous reads by the host processor and the peripheral controller for indicating to the host processor that the resource is unavailable thus giving priority to the peripheral controller. The semaphore bit may be reset by write signals from either the peripheral controller or the host processor.

Instruction register sequence decoder for microprogrammed data processor and method

Abstract: A data processor which includes an instruction register for storing a macroinstruction to be executed, a decoder responsive to the stored macroinstruction for generating two or more starting addresses, and a selector which receives the starting addresses generated by the decoder and which selects one of the starting addresses as a next address in response to one or more selection signals. The data processor also includes a control structure which receives the next address chosen by the selector and which selects one of the starting addresses as a next address in response to one or more selection signals. The data processor also icludes a control structure which receives the next address chosen by the selector and which, in response to the next address, derives the selection signals to which the selector will respond in order to select a subsequent next address. The decoder and selector may be adapted such that an additional starting address is provided to the selector such that the selector chooses this additional starting address regardless of the condition of the one or more selection signals generated by the control structure. The control structure may be implemented with a microprogrammed control store containing a plurality of microinstruction routines each having a corresponding starting address such that the starting addresses generated by the decoder correspond to various microinstruction routines contained in the microprogrammed control store.

Differential to single-ended converter utilizing inverted transistors

Abstract: A differential to single-ended converter circuit is disclosed which utilizes integrated injection logic device geometrics to significantly reduce the area required to fabricate the converter within an integrated circuit. Inverted transistor operation and multiple collector output terminals allow the converter circuit to directly drive integrated injection logic circuitry which may be fabricated within the same integrated circuit chip. When used in conjunction with a voltage comparator circuit, the differential to single-ended converter circuit maintains the offset associated with the comparator circuit at a minimum despite variations in operating temperature and variations in integrated circuit processing.

Linearized digital phase and frequency detector

Abstract: A digital phase and frequency detector is capable of providing a linearized transfer function. The digital phase and frequency detector includes two latches each receiving an input and each providing an output. The output of the latches is combined by a logic gate to generate a reset signal. The linearization is a result of providing a delay to the reset signal. The reset signal is used to reset the two latches within the phase and frequency comparator. This improved phase and frequency comparator eliminates non-linearities which would otherwise be inherent in its transfer function and thereby degrade performance of phase-locked systems employing the comparator. The phase and frequency detector is easily manufactured as an integrated circuit and does not require any external signals in order to eliminate the non-linear region.

Microprocessor interrupt processing

Abstract: An integrated circuit data processor receives interrupt level signals from external circuitry which represent a priority level associated with the external circuitry. These signals are compared with signals representing the current operating level of the processor, and an interrupt pending output is generated if (1) the priority level is higher than the operating level; or (2) a maximum priority level is received. Upon the occurrence of the interrupt pending output, the current instruction program is interrupted, and an instruction program associated with the external circuitry is executed. The processor transmits a signal back to the external circuitry indicating that the interrupt request has been granted and receives a vector number from the external circuitry. A first acknowledgment signal from the external circuitry causes the vector number to be latched in the processor. A second acknowledgment signal from the external circuitry causes a vector to be internally generated. Error circuitry is provided to detect spurious interrupts.

Asynchronous event prioritizing circuit

Abstract: A prioritizing circuit is provided for arbitrating between asynchronously occurring memory access request and memory refresh request signals to a dynamic RAM memory module. The circuit includes a latch circuit (20), a latch control circuit (21), and priority logic (22). The latch circuit is responsive to the request signals and latches the state of both signals upon receipt of a strobe signal generated by the latch control circuit. The latch control circuit generates the strobe signal upon detection of the first access request signal transmitted to the latch circuit at a predetermined logic level. To arbitrate priority between request signals occurring substantially simultaneously, the priority logic includes a combinatorial logic network responsive to the outputs of the latch circuit for generating a grant signal corresponding to the request signal having the higher priority. A delay circuit (23) provides a delayed strobe signal input to the priority logic, so that the combinatorial logic is only enabled after an appropriate settling time.

Bar code scanner interface

Abstract: The positive and negative peak detectors in the interface are reset during each input signal cycle and the reference level used for comparison is switched from one level to another to improve decoding accuracy, with each level determined by the previous two peaks. The input signal is DC coupled and DC offset. The scanner light source is pulsed by a low duty cycle power source if code is not being scanned. The circuit is applicable for digitizing any analog signal with varying amplitudes and/or DC levels and is adaptable to microprocessor control.

Phase-encoded data signal demodulator

Abstract: A demodulator is described for demodulating phase-encoded data signals transmitted on a noisy communication channel, such as, for example, radio communication channels of a radio communication system. The demodulator includes a digital phase-locked loop for phase-locking to the mid-bit transitions of the phase-encoded data signal, which, in the preferred embodiment is encoded according to the well known Manchester coding format, and further includes demodulating circuitry for sampling the phase-encoded data signal a predetermind number of times, weighting the samples according to predetermined weighting factors, totalizing the weighted samples for each bit interval and comparing the totalized samples to a predetermined threshold value for ascertaining the logical state of each bit of the phase-encoded data signal. For example, if the magnitude of the totalized samples is greater than or equal to the threshold value, a logical one state may be provided for the decoded data signal, and, if the magnitude of the totalized samples is less than the threshold value, a logical zero state may be provided for the decoded data signal. In preferred embodiments of the present invention, the weighting factors assigned to each sample may be either binary weighted or sine weighted, although any suitable weighting factors may be utilized depending on the characteristics of the phase-encoded data signal. The phase-encoded data signal demodulator embodying the present invention is particularly well adapted for demodulating high speed, phase-encoded data signals transmitted over radio channels to mobile and portable stations of a radio communication system.

Universal interface circuit for synchronous and asynchronous buses

Abstract: A universal bus interface circuit can be used in conjunction with either synchronous or asynchronous bus systems. An input terminal is monitored to determine if the bus is synchronous or asynchronous. If the bus is asynchronous, a synchronization circuit generates a synchronous control signal for internal use from an asynchronous select signal. The synchronization circuit also generates an asynchronous hand-shake or acknowledge signal which is applied to the input terminal to indicate completion of the operation. The input terminal is monitored by a host processor.

Method and means of clock recovery in a received stream of digital data

Abstract: Clock recovery in a received stream of digital data is effected by generating a high-speed clock pulse that is applied to a programmable divider to produce a recovered clock pulse. Comparison of the phase of the recovered clock pulse with that of a received signal causes accumulation of fast or slow counts that increase or decrease the division of the programmable divider to restore synchronism. The accumulated count is reduced for rapid recovery when the two signals are unsynchronized.

Data security module

Abstract: A data security module for encrypting and decrypting computer data contains, in addition to the encryption logic, interface logic to allow direct memory access to a computer. The security module sits as a computer peripheral device and after being instructed as to the location and quantity of data by the computer, accesses the data directly from the computer memory without disturbing the processor to provide parallel encryption or decryption of computer memory data.

Amplifier protection circuit

Abstract: A protection circuit for a transmitter amplifier which provides power leveling and controls transmitter output power as a function of the ratio of reflected power to forward power. The circuit senses forward power level and develops a first voltage which is compared with the reference voltage to provide a control voltage which controls the power developed by the transmitter amplifier. Reflected power is sensed and a second voltage is developed which is compared to a portion of the first voltage and causes a reduction in the reference voltage when the reflected power to forward power ratio exceeds a predetermined level.

Programmable multifrequency tone receiver

Abstract: A multifrequency tone receiver (100) for detecting simultaneous tone signals in a sampled digital signal. The tone receiver (100) includes a microprogrammed sequence controller (101 and Fig. 3B), a time-multiplexed digital filter (102 and Fig. 3C) and a signal processing microcomputer (103 and Fig. 3A). For each sample of the digital signal, the sequence controller (101) is programmed to time multiplex the digital filter (102) for performing three cascaded second order filtering operations (two bandpass filter operations and one low pass filter operation as shown in Fig. 2) for each of six tone signals to provide corresponding energy estimates and one additional filtering operation to provide a total energy estimate. The signal processing microcomputer (103) processes (per flowchart in Fig. 7) a number of sets of the seven energy estimates and provides an indication when a multifrequency tone pair has been detected. The digital filter (102), when enabled by a filter start signal from the sequence controller (101), asynchronously performs a signal multiplication-like filtering operation to implement each second-order filter, and provides a filter done signal upon completion of the filtering operation. Full-wave rectifying capability is provided during low pass filtering operations by logically complementing (gate 361 in Fig. 3C) the digital filter input signal. Limit cycles may be suppressed in the digital filter output signal by rounding the output signal and clamping (gates 365-368 in Fig. 3C) positive and negative overflows to the largest allowable positive and negative signals, respectively. The tone receiver (100) may be advantageously utilized in a PCM communication system for detecting multifrequency tone signalling used for dialing and supervisory control. Moreover, the inventive tone receiver (100) may be adapted to receive many different types of tone signalling simply by changing firmware (Tables I and IV) therewithin.

Land-mobile satellite excess path loss measurements

Abstract: An experiment conducted with the ATS-6 satellite to determine the additional path loss over free-space loss experienced by land-mobile communication links is described. This excess path loss is measured as a function of 1) local environment, 2) vehicle heading, 3) link frequency, 4) satellite elevation angle, and 5) street side. A statistical description of excess loss developed from the data shows that the first two parameters dominate. Excess path loss on the order of 25 dB is typical in urban situations, but decreases to under 10 dB in suburban/rural areas. Spaced antenna selection diversity is found to provide only a slight decrease (4 dB, typically) in the urban excess path loss observed. Level crossing rates are deprsessed in satellite links relative to those of Rayleigh-faded terrestrial links, but increases in average fade durations tend to offset that advantage. The measurements show that the excess path loss difference between 860- MHz links and 1550-MHz links is generally negligible.

Advanced data link controller having a plurality of multi-bit status registers

Abstract: A bit-oriented data link controller provides the interface between a microcomputer or terminal and a data communications link. The data link controller is capable of accommodating the three most commonly available bit-oriented data link control protocols, namely SDLC, HDLC, and ADCCP. The data link controller provides the data communications interface for both primary and secondary stations in stand-alone, polling, and loop configurations.

Soft quantizer for fm radio binary digital signaling

Abstract: A soft quantizer for assigning numerical weights to hard quantized output bits of a binary digital detector in a digital receiver based on the noise energy level of the received baseband data. An analog signal, derived from the discriminator noise level, is digitized by an analog to digital converter for use as an address to look up predetermined numerical weights for soft quantized values in a memory table. The addressed numerical weights are combined with the hard quantized output bits of the digital detector to generate soft quantized data values.

Solid-state voltage reference providing a regulated voltage having a high magnitude

Abstract: A two transistor voltage reference circuit controls the ratio of the current densities of two transistors by a negative feedback loop. A voltage corresponding to the difference in the base-to-emitter voltages of the two transistors is developed which has a positive temperature coefficient (TC) and which is connected in series with the base-to-emitter voltage of one of the two transistors having a negative TC. The circuit parameters are selected so that the resultant combined voltage has a predetermined, composite TC. A zener diode is included in the negative feedback loop and arranged to have a TC which cancels the predetermined composite TC to develop a reference voltage having a high magnitude that has minimal variation with temperature change.

Method and means of minimizing simulcast distortion in a receiver when using a same-frequency repeater

Abstract: Simulcast distortion in a receiver when using a same-frequency repeater is minimized by applying double modulation to a signal that is broadcast to the same-frequency repeater. A voice signal is applied without delay as AM on a carrier to a modulation index of up to 30%, and the same signal is also applied as FM on the same carrier with a time delay equal to the time delay in the same-frequency repeater. The same-frequency repeater detects the AM and applies the detected signal as FM on a carrier that is rebroadcast. Received FM signals are thus delayed by substantially the same amount whether they are received from the original broadcast or the same-frequency repeater.

Interface adapter architecture

Abstract: A unique interface adapter is described which includes circuitry for recovering a clock signal and a non-return-to-zero (NRZ) data signal from a data signal transmitted on two forward data signals. The NRZ data signal is shifted into a receiving register, where address circuitry decodes the address portion of the data signal to provide a chip select signal and control circuitry decodes the control portion of the data signal to provide a register select signal, read/write signal and bus sense signal. The register select signal determines whether an output register or a data direction register is to be loaded in response to the read/write signal with the data portion of the data signal. The binary states of the data direction register determine which ones of the interface signals are to be output signals, and enable corresponding output register signals to be applied to the interface signals by way of transmission gates. While a data signal is being received on the forward data signals, the interface signals are loaded into a transmitting register and, in response to the chip select signal and clock signal, serially applied to a return data signal. The unique interface adapter may be advantageously utilized in any application where it is necessary to remotely control a plurality of interface lines with a minimum number of signal lines.

Alu and condition code control unit for data processor

Abstract: A data processor which is adapted for microprogrammed operation has a control store includes an ALU and condition code control unit for controlling operations performed by an arithmetic-logic unit within the execution unit of the data processor and for controlling the setting of the condition code bits in a status register. The ALU and condition code control unit is arranged in a row and column format. A decoder coupled to a macroinstruction register selects a row which is selected over an entire period that is required to execute macroinstruction. The row corresponds to a set of operations and condition code settings associated with a particular macroinstruction. The control store output provides information for selecting the proper column during each microcycle used to execute the macroinstruction. ALU function control signals and the condition code control signals are selected simultaneously according to the selected row and column.

Keyboard and display interface adapter architecture

Abstract: A unique interface adapter is coupled to a microprocessor by a three-wire self-clocking serial data bus for accommodating a twenty-key keyboard and an eight-digit display. The interface adapter includes circuitry for recovering a clock signal and a non-return-to-zero (NRZ) data signal from the data signal transmitted on two forward signal lines of the serial data bus. The NRZ data signal is shifted into a receiving register, where address circuitry decodes the address portion of the data signal to provide a chip select signal and control circuitry decodes the control portion of the data signal to provide a register select signal, read/write signal and bus sense signal. The register select signal determines whether a control register or display register is to be loaded in response to the read/write signal with the data portion of the data signal. The control register signals activate four status indicating LED's, apply power to the display, select between a ten or sixteen digit display, enable an audio tone generator and reset a status bit flip-flop. The display register receives two BCD digits which are stored in a display memory. The keys of the keyboard are scanned at the same time digits read-out from the display memory are being applied to the display. The signals identifying the row and column of activated keys are provided in a return signal line of the serial data bus.