Showing papers by "Teradyne published in 2004"

System optimization with component reliability estimation uncertainty: a multi-criteria approach

Abstract: Summary & Conclusions-This paper addresses system reliability optimization when component reliability estimates are treated as random variables with estimation uncertainty. System reliability optimization algorithms generally assume that component reliability values are known exactly, i.e., they are deterministic. In practice, that is rarely the case. For risk-averse system design, the estimation uncertainty, propagated from the component estimates, may result in unacceptable estimation uncertainty at the system-level. The system design problem is thus formulated with multiple objectives: (1) to maximize the system reliability estimate, and (2) to minimize its associated variance. This formulation of the reliability optimization is new, and the resulting solutions offer a unique perspective on system design. Once formulated in this manner, standard multiple objective concepts, including Pareto optimality, were used to determine solutions. Pareto optimality is an attractive alternative for this type of problem. It provides decision-makers the flexibility to choose the best-compromise solution. Pareto optimal solutions were found by solving a series of weighted objective problems with incrementally varied weights. Several sample systems are solved to demonstrate the approach presented in this paper. The first example is a hypothetical series-parallel system, and the second example is the fault tolerant distributed system architecture for a voice recognition system. The results indicate that significantly different designs are obtained when the formulation incorporates estimation uncertainty. If decision-makers are risk averse, and wish to consider estimation uncertainty, previously available methodologies are likely to be inadequate.

Electrical connector incorporating passive circuit elements

Abstract: An electrical connector that electrically connects a first printed circuit board and a second printed circuit board is disclosed, where the electrical connector in the preferred embodiment includes: (a) an insulative housing; (b) a plurality of signal conductors, with at least a portion of each of the plurality of signal conductors disposed within the insulative housing; (c) each of the plurality of signal conductors having a first contact end, a second contact end and an intermediate portion therebetween; and (d) a passive circuit element electrically connected to the intermediate portion of each of the plurality of signal conductors, where the passive circuit element is housed in an insulative package and includes at least a capacitor or an inductor.

Modular liquid cooling of electronic assemblies

Abstract: An electronic system includes an array of electronic assemblies at a first location within a system. An array of liquid cooling assemblies is placed at a second location within the system. Hoses or other liquid transport pathways connect the cooling assemblies to the electronic assemblies, for cooling the electronic assemblies. As more electronic assemblies are added to the system, additional cooling assemblies may be provided to manage the increased thermal demands.

Transfer functions for the reference clock jitter in a serial link: theory and applications

Abstract: Transfer functions for the reference clock jitter in a serial link such as the PCI express 100 MHz reference clock are established for various clock and data recovery circuits (CDRCs). In addition, mathematical interrelationships between phase, period, and cycle-to-cycle jitter are established and phase jitter is used with the jitter transfer function. Numerical simulations are carried out for these transfer functions. Relevant eye-closure/total jitter at a certain bit error rate (BER) level for the receiver is estimated by applying these jitter transfer functions to the measured phase jitter of the reference clock over a range of transfer function parameters. Implications of this new development to serial link reference clock testing and specification formulation are discussed.

Methods of manufacturing an electrical connector incorporating passive circuit elements

Abstract: A process for manufacturing an electrical connector is described. In the preferred embodiment, the process includes the following steps: (a) providing a lead frame that has a plurality of signal conductors, where each of the signal conductors has a first contact end, a second contact end and an intermediate portion therebetween; (b) providing at least a segment of the intermediate portion of the signal conductors with solder wettable material; (c) providing an insulative housing around at least a portion of each of the plurality of signal conductors, the insulative housing providing openings through which an exposed area of each of the signal conductors is accessible, where the exposed area includes the segment of the intermediate portion with solder wettable material; (d) cutting and removing a portion of the exposed area of the signal conductors such that only a portion of the exposed area remains; and (e) attaching a passive circuit element to the remaining portion of the exposed area of each of the signal conductors.

Method and system for testing semiconductor devices

Abstract: A semiconductor device tester includes a parametric measurement unit (PMU) stage for producing a DC test signal and a pin electronics (PE) stage for producing an AC test signal to test a semiconductor device. A driver circuit is capable of providing a version of the DC test signal and a version of the AC test signal to the semiconductor device.

Interface apparatus for semiconductor device tester

Abstract: A signal interface to connect a semiconductor tester to a device under test. The Interface includes a generic component and customized component. The generic component includes multiple copies of electronic elements that can be connected in signal paths between the tester and the device under test. The customized component is constructed for a specific device under test and provides connections between generic contact points on the generic component and test points on the device under test. In addition, the customized component has conductive members that can be used to interconnect the electronic elements on the generic component. The connections configure the electronic elements into signal conditioning circuitry, thereby providing signal paths through the interface that are compatible with the I/O characteristics of specific test points on a device under test. The generic and the customized components may be fabricated on semiconductor wafers.

Method of measuring duty cycle

Abstract: A method for measuring the duty cycle of a signal. The method is fast enough to allow duty cycle measurements of semi-conductor components during production. The method can also be performed inexpensively using automatic test equipment. A comparator in a digital channel is used to sense the state of an input signal at multiple points across the period of the signal. Fail processing circuitry within the tester is used to count the number of samples for which the input signal is in a logic HI state. This value is scaled by the total number of samples taken to produce a single number indicative of the duty cycle of the signal.

Flexible optical interconnection system

Abstract: An optical connector system assembled from modular components. These components include connector modules that position ferrules for mating and providing fine alignment to fibers. The modules are assembled to support members to form connectors of various sizes. Mounting modules are attached to the support members. Various shaped mounting modules are provided, allowing connectors to be assembled for various configurations, such as a matrix configuration, a parallel board-to-board configuration or a panel mount configuration.

Efficient switching architecture with reduced stub lengths

Abstract: A switching topology for communicating signals in an automatic test system includes a plurality of switching circuits each for selectively passing signals or crossing signals. Switching circuits are connected together such that each node of any switching circuit connects to no more than one node of any other switching circuit. This topology offers improved signal integrity, reduced cost, and reduced space as compared with conventional, matrix-style switching topologies.

Test system with differential signal measurement

Abstract: A test system with easy to fabricate hardware to make measurements on differential signals. The two legs of a differential signal are applied to a comparator. A variable bias is introduced into the comparison operation. By taking multiple measurements with different bias levels, the level of the differential signal may be determined. The time of measurements relative to the start of the signal can be varied to allow plots of the signal to be made. Variability of the signal caused by noise can be measured by collecting sets of data points with the same bias level at the same relative time. Circuitry for introducing bias into the comparison is disclosed that allows measurements to be made with a pre-packaged, commercially available high speed comparator.

Precise time measurement apparatus and method

Abstract: A time measurement system that uses two signals generated by direct digital synthesis. The generated signals have the same frequency but different phase. One signal is used to identify the start of the measurement interval and the other signal is used to identify a measurement window in which a signal indicating the end of the measured interval might be detected. The time measurement system is used as part of a time domain reflectometry (TDR) system. An incident pulse is synchronized to the first signal and launched down on a line. In the measurement window, the signal on the line is compared to a threshold value to determine whether the pulse has been reflected and traveled back to the source. By iteratively repeating the measurement with a different measurement window, the time of arrival of the reflected pulse can be determined. This time domain reflectometry approach is incorporated into automatic test equipment for testing semiconductor devices and is used to calibrate the test equipment.

Digital phase detector

Abstract: A high performance phase detector includes a local digital oscillator for generating a digital reference signal of programmable frequency and phase. The phase detector accumulates a difference in phase between the digital reference signal and a sampled input signal to produce a measure of phase error. The phase detector can be advantageously used in a frequency synthesizer to produce signals with low phase noise and accurate phase control. Synthesizers of this type can further be used to as building blocks in ATE systems and other electronic systems for generating low jitter clocks and waveforms.

Vehicle communications interface

Abstract: An improved vehicle communications interface (VCI) is both economical and readily adaptable for running new software. The improved VCI includes a server coupled to a bank of processors. The server can communicate with a host, and the processors can communicate with different vehicle networks. Each processor includes a state machine and a media access controller for a particular vehicle network. The state machine identifies incoming messages that require real time responses and provides the requisite responses directly back to the network, without involvement of the server. Real time requirements of the server are thus relieved, allowing the server to run a non-real time, mainstream operating system for which new product software is readily available.

Automatic test system with easily modified software

Abstract: An automatic test system, such as might be used to test semiconductor devices as part of their manufacture. The test system uses instruments to generate and measure test signals. The automatic test system has a hardware and software architecture that allows instruments to be added to the test system after it is manufactures. The software is segregated into instrument specific and instrument independent software. Predefined interfaces to the software components allow for easy integration of instruments into the test system and also easy reuse of the software as the physical implementation of the test system or the instruments changes form tester to tester in a product family.

Time measurement method using quadrature sine waves

Abstract: A time measurement circuit includes N time stamping units that each includes a dual sinusoid interpolator for achieving high timing resolution. The time measurement circuit is capable of time stamping input signals at a high re-trigger rate, and is thus well suited for quickly measuring the timing jitter of test signals in automatic test systems.

Synchronization between low frequency and high frequency digital signals

Abstract: A synchronization circuit for synchronizing low frequency digital circuitry and high frequency digital circuitry. The synchronization circuit produces an ordered series of clocks from the high-frequency digital clock. The clocks have a deterministic time relationship, with at least one clock having a period longer than the timing uncertainty associated with a synchronization signal. The synchronization signal is passed through a chain of latches, each one clocked by one of the divided down clocks with successively higher frequency. These latches align the synchronization signal with the clocks produced by the clock divider, ultimately aligning the synchronization signal with the high frequency clock. This synchronization circuit is described in connection with automatic test equipment used in the manufacture of semiconductor devices.

Using parametric measurement units as a source of power for a device under test

Abstract: An apparatus for providing current to a device under test includes a first parametric measurement unit configured to provide current to the device, and a second parametric measurement unit configured to provide current to the device The current from the second parametric measurement unit augments the current from the first parametric measurement unit at the device

Rear-mounted gimbal for supporting test head

Abstract: A manipulator for supporting heavy as well as lighter test heads in a small footprint includes a body and an interface for supporting a test head from behind. The interface includes a first portion fixedly attached to the body and a second portion fixedly attached to the rear of the test head. The first and second portions of the interface are rotatably coupled together to allow rotation of the test head about its approximate center of mass. Although the weight of the test head is entirely borne from the rear, the test head can still be moved with relatively little applied force, thereby satisfying the requirements for compliant docking.

Connector system for optical wave guides

Abstract: An optical connector system joining waveguides in two printed circuit boards. A flexible optical conductor is connected at one end to one of the boards. The flexible conductor includes at its free end an alignment structure that provides a separable, low loss interface to an alignment structure coupled to the waveguide on the other board. The ends of the waveguides are enclosed in housings that protect the waveguides from abrasion and contaminates, but expose the waveguides when the connectors mate.

Liquid cooling high power compact electronics

Abstract: Conventional electronics liquid cooling are used in automatic test equipment (ATE) and military equipment, it is implemented using blind-mate fluid disconnects packaged alongside the card edge connectors, or using hoses and manual latching fluid disconnects. This paper describe a novel rack-mount liquid cooling packaging architecture. This arrangement utilizes manual latching fluid disconnects, so that the fluid transport lines to the electronics below are also front-side accessible. The system enables single or two-phase heat transfer between the fluid and the electronics as long as the heat load ensures only liquid passes to the pump. The liquid cooling system itself relies on the ambient air to dissipate the heat; it only transports the heat to a rack location where it easier to dissipate the heat.

Thermally enhanced pressure regulation of electronics cooling systems

Abstract: A two-phase cooling system operated at atmospheric pressure. A reservoir containing cooling fluid has a stack that is vented to the atmosphere. The stack is shaped to allow condensation of substantially all of the cooling fluid in vapor form entering the stack. Condensation may be enhanced by cooling the stack, such as with flowing air along the outer walls of the stack or placing a thermoelectric device in contact with the stack. The system provides high thermal capacity but is easy to use and service.

Method for digital bus testing

Abstract: An interface for a bus test instrument is readily adaptable for testing a wide range of bus types. The interface includes a pair of transmit lines and a pair of receive lines. A transmitting circuit is adaptable for transmitting either single-ended or differential signals over the transmit lines, and at least one receiving circuit is adaptable for receiving either single-ended or differential signals from either the receive lines or the transmit lines. The flexible interface allows the testing of single-ended and differential busses, as well as busses that support both unidirectional and bidirectional communication.

Backplane with routing to reduce layer count

Abstract: An electronic system having a backplane designed for efficient routing of signal traces. The system includes two or more daughter cards that are connected to multiple other daughter cards in the system. These daughter cards are mounted centrally to the backplane in the system. Connections between those two daughter cards and the backplane are made through electrical connectors that are distributed in columns along the length of the daughter cards. The connectors are positioned with space between the connectors. The space forms routing channels such that signals that must be connected to the central cards from a daughter cards on either side may be routed through the routing channels.

Test plan allocation to minimize system reliability estimation variability

Abstract: A new methodology is presented to allocate testing units to the different components within a system when the system configuration is fixed and there are budgetary constraints limiting the amount of testing. The objective is to allocate additional testing units so that the variance of the system reliability estimate, at the conclusion of testing, will be minimized. Testing at the component-level decreases the variance of the component reliability estimate, which then decreases the system reliability estimate variance. The difficulty is to decide which components to test given the system-level implications of component reliability estimation. The results are enlightening because the components that most directly affect the system reliability estimation variance are often not those components with the highest initial uncertainty. The approach presented here can be applied to any system structure that can be decomposed into a series-parallel or parallel-series system with independent component reliability estimates. It is demonstrated using a series-parallel system as an example. The planned testing is to be allocated and conducted iteratively in distinct sequential testing runs so that the component and system reliability estimates improve as the overall testing progresses. For each run, a nonlinear programming problem must be solved based on the results of all previous runs. The testing allocation process is demonstrated on two examples.

Current mirror compensation using channel length modulation

Abstract: A current compensation circuit for use with a current mirror circuit is disclosed. The current mirror circuit has a current path defined by a first programmable current mirror stage driving a first fanout current mirror stage. The first programmable current mirror stage includes at least one transistor with a channel length exhibiting a first channel length modulation factor λ1. The first fanout current mirror stage connects to a supply voltage source. The current compensation circuit comprises a supply voltage current mirror coupled to the supply voltage source and has a current output coupled to the current path. The compensation circuit further includes a second programmable current mirror coupled in series to the supply voltage current mirror and including at least one transistor with a channel length exhibiting a channel length modulation factor λ2. The second channel length modulation factor λ2 is larger than the first channel length modulation factor λ1. As a result, the first programmable current mirror and the second programmable current mirror cooperate to maintain a bias current through the first fanout current mirror stage substantially independent of changes in the supply voltage.

Non-deterministic DUT behavior during functional testing of high speed serial busses: challenges and solutions

Abstract: The characteristics defining non-determinism for PCI Express busses are explored. The RapidIO/sup /spl reg// bus is used as a point of comparison. ATE architecture is proposed to significantly reduce the yield and throughput impact of random output. A specific architecture is explored and proposed for real-time pass/fail analysis of HSS data streams in the ATE environment.

Apparatus and method for calibrating equipment for high frequency measurements

Abstract: Calibration standards for accurate high frequency or wide bandwidth calibration measurements. A “short” or “reflect” standard is formed in a printed circuit board from a conductive coating on a generally planar surface. The conductive coating connects a signal trace to one or more ground planes. The generally planar surface is at least as wide as the signal trace and is preferably several times wider than the signal trace to provide a short standard with properties uniform over a wide frequency range. The short standard is incorporated into a printed circuit upon which a device under test is to be mounted. Connections to the short standard are made through components equivalent to components used to connect a device under test. When a through and line standard are added to the same board, the test board contains all the standards needed for a TRL calibration.