Turku Centre for Computer Science

About: Turku Centre for Computer Science is a facility organization based out in Turku, Finland. It is known for research contribution in the topics: Decidability & Word (group theory). The organization has 382 authors who have published 1027 publications receiving 19560 citations.

From Watson-Crick L systems to Darwinian P systems

Abstract: Watson-Crick L systems are language generating devices making use of Watson-Crick complementarity, a fundamental concept of DNA computing. These devices are Lindenmayer systems enriched with a trigger for complementarity transition: if a ``bad'' string is obtained, then the derivation continues with its complement which is always a ``good'' string. Membrane systems or P systems are distributed parallel computing models which were abstracted from the structure and the way of functioning of living cells. In this paper, we first interpret the results known about the computational completeness of Watson-Crick E0L systems in terms of membrane systems, then we introduce a related way of controlling the evolution in P systems, by using the triggers not in the operational manner (i.e., turning to the complement in a ``bad'' configuration), but in a ``Darwinian'' sense: if a ``bad'' configuration is reached, then the system ``dies'', that is, no result is obtained. The triggers (actually, the checkers) are given as finite state multiset automata. We investigate the computational power of these P systems. Their computational completeness is proved, even for systems with non-cooperative rules, working in the non-synchronized way, and controlled by only two finite state checkers; if the systems work in the synchronized mode, then one checker for each system suffices to obtain the computational completeness.

Lightweight Framework for Runtime Updating of C-Based Software in Embedded Systems

Abstract: Software updates in embedded systems are typically performed by bringing the system to stop, replacing the software and restarting the system. This process can in certain cases be very time consuming and costly, which leads to less frequent software updates. In order to establish both long uptime and up-to-date software, the software must be updated during runtime. This paper presents a runtime updating framework for embedded systems capable of replacing parts of software without stopping the system. The framework is based on FreeRTOS and mechanisms have been added to dynamically link and re-link FreeRTOS tasks to the system during runtime. Our framework enables the programmer to easily create updatable software with simple annotations to the program. Experiments demonstrate the benefits of updating software during runtime with an acceptable overhead when transferring the application state.

Efficient bytecode optimizations for a multicore Java co-processor system

Abstract: As the bytecode produced by the Java compiler is unoptimized, the bytecode generated from certain types of idiomatic Java code is inefficient for execution in an interpreter. This effect is amplified in a co-processor system, in which a single processor must process heap accesses and virtual method calls from multiple threads. Two types of optimizations are presented which can be performed directly on bytecode during class loading and which do not require a large amount of processing time. These optimizations are shown to improve performance greatly, up to 29 % in the Embedded Caffeinemark Benchmark suite. Even higher improvements were measured in multithreaded programs.

SL - A Structural Hardware Design Language

Abstract: SL is a simple language designed to improve the productivity of hardware design. It is easy to use and it adopts reusable word-level and bit-level descriptions. This results in concise and easily grasped descriptions which give a good overview of the design. Used together with our SLAVE compiler, SL offers a fast way to produce complicated structural VHDL-code. This structural VHDL-code can then be used by Velab VHDL elaborator in order to produce a netlist for Xilinx XC6200 FPGA.

A Polynomial Bound for Certain Cases of the D0L Sequence Equivalence Problem

Abstract: All known bounds for the D0L sequence equivalence problem in the general case are huge. We give a bound for polynomially bounded PD0L systems which is less than quartic with respect to the cardinality of the alphabet and the size of the systems.