Showing papers in "IEEE Transactions on Semiconductor Manufacturing in 2000"

Modeling of interconnect capacitance, delay, and crosstalk in VLSI

Abstract: Increasing complexity in VLSI circuits makes metal interconnection a significant factor affecting circuit performance. In this paper, we first develop new closed-form capacitance formulas for two major structures in VLSI, namely: (1) parallel lines on a plane and (2) wires between two planes, by considering the electrical flux to adjacent wires and to ground separately. We then further derive closed-form solutions for the delay and crosstalk noise. The capacitance models agree well with numerical solutions of three-dimensional (3-D) Poisson equation as well as measurement data. The delay and crosstalk models agree well with SPICE simulations.

A neural-network approach to recognize defect spatial pattern in semiconductor fabrication

Abstract: Yield enhancement in semiconductor fabrication is important. Even though IC yield loss may be attributed to many problems, the existence of defects on the wafer is one of the main causes. When the defects on the wafer form spatial patterns, it is usually a clue for the identification of equipment problems or process variations. This research intends to develop an intelligent system, which will recognize defect spatial patterns to aid in the diagnosis of failure causes. The neural-network architecture named adaptive resonance theory network 1 (ART1) was adopted for this purpose. Actual data obtained from a semiconductor manufacturing company in Taiwan were used in experiments with the proposed system. Comparison between ART1 and another unsupervised neural network, self-organizing map (SOM), was also conducted. The results show that ART1 architecture can recognize the similar defect spatial patterns more easily and correctly.

Level-specific lithography optimization for 1-Gb DRAM

Abstract: A general level-specific lithography optimization methodology is applied to the critical levels of a 1-Gb DRAM design at 175- and 150-nm ground rules. This three-step methodology-ruling out inapplicable approaches by physical principles, selecting promising techniques by simulation, and determining actual process window by experimentation-is based on process latitude quantification using the total window metric. The optimal lithography strategy is pattern specific, depending on the illumination configuration, pattern shape and size, mask technology, mask tone, and photoresist characteristics. These large numbers of lithography possibilities are efficiently evaluated by an accurate photoresist development bias model. Resolution enhancement techniques such as phase-shifting masks, annular illumination and optical proximity correction are essential in enlarging the inadequate process latitude of conventional lithography.

Fault detection of plasma etchers using optical emission spectra

Abstract: The objective of this paper is to investigate the suitability of using optical emission spectroscopy (OES) for the fault detection and classification of plasma etchers. The OES sensor system used in this study can collect spectra at up to 512 different wavelengths. Multiple scans of the spectra are taken from a wafer, and the spectra data are available for multiple wafers. As a result, the amount of the OES data is typically large. This poses a difficulty in extracting relevant information for fault detection and classification. In this paper, we propose the use of multiway principal component analysis (PCA) to analyze the sensitivity of the multiple scans within a wafer with respect to typical faults such as etch stop, which is a fault that occurs when the polymer deposition rate is larger than the etch rate. Several PCA-based schemes are tested for the purpose of fault detection and wavelength selection. A sphere criterion is proposed for wavelength selection and compared with an existing method in the literature. To construct the final monitoring model, the OES data of selected wavelengths are properly scaled to calculate fault detection indices. Reduction in the number of wavelengths implies reduced cost for implementing the fault detection system. All experiments are conducted on an Applied Materials 5300 oxide etcher at Advanced Micro Devices (AMD) in Austin, TX.

Adaptive optimization of run-to-run controllers: the EWMA example

Abstract: This paper presents a recursive scheme for optimizing the gain of an exponentially weighted moving average (EWMA) controller under stability constraints. The objective is to minimize the asymptotic mean square error in the output with minimal a priori information. The algorithm hinges on a simple representation of the optimal EWMA gain. Both step and drift disturbances are considered. It is shown that the gain sequence generated by the algorithm always yields a stable system. Furthermore, this sequence is shown to converge to a suboptimal value. Extensions to the algorithm to the case where there is model uncertainty are also presented. The algorithm is verified via simulation. Data from a manufacturing implementation are presented.

A new method for treating fluorine wastewater to reduce sludge and running costs

Abstract: Reduction of the sludge generated in fluorine wastewater treatment is a critical problem for the semiconductor industry. We have developed a new method for treating fluorine wastewater in order to reduce sludge and running costs. This method utilizes a small amount of Al(OH)/sub 3/ not only as an aggregator for CaF/sub 2/ generated from fluoride ions in the wastewater but also as an effective fluorine adsorbent. The Al(OH)/sub 3/ as fluorine adsorbent is used repeatedly through an AI(OH)3 reclamation process. This method can effectively treat the concentrated fluorine wastewater to achieve an exceedingly low concentration in one-step treatment. We constructed a practical treatment system using this method by modifying part of an existing conventional system. This new treatment system is able to reduce both the total sludge and running costs to about one-tenth those of a conventional system.

Implementation of modeling and simulation in semiconductor wafer fabrication with time constraints between wet etch and furnace operations

Abstract: In semiconductor wafer fabrication, time constraints between process steps in furnace and wet etch make it difficult to achieve cycle time targets and maximize machine utilization. For capacity planning, it is difficult to estimate the impact of these time constraints on the machine capacity. Infineon Technologies Dresden has conducted a study using discrete event simulation, to investigate the actual situation in the factory and to identify recommendations to eliminate or to reduce the impart of time constraints. The work in this paper yields a two-day reduction in total cycle time after implementation of findings in the factory.

Analysis of the impact of process variations on clock skew

Abstract: In this paper, we analyze the impact of process variations on the clock skew of VLSI circuits designed in deep submicrometer technologies. With smaller feature size, the utilization of a dense buffering scheme has been proposed in order to realize efficient and noise-immune clock distribution networks. However, the local variance of MOSFET electrical parameters, such as V/sub T/ and I/sub DSS/, increases with scaling of device dimensions, thus causing large intradie variability of the timing properties of clock buffers. As a consequence, we expect process variations to be a significant source of clock skew in deep submicrometer technologies. In order to accurately verify this hypothesis, we applied advanced statistical simulation techniques and accurate mismatch measurement data in order to thoroughly characterize the impact of intradie variations on industrial clock distribution networks. The comparison with Monte Carlo simulations performed by neglecting the effect of mismatch confirmed that local device variations play a crucial role in the design and sizing of the clock distribution network.

Low open-area endpoint detection using a PCA-based T/sup 2/ statistic and Q statistic on optical emission spectroscopy measurements

Abstract: Examines an approach for automatically identifying endpoint (the completion in etch of a thin film) during plasma etching of low open area wafers. Because many end-pointing techniques use a few manually selected wavelengths or simply time the etch, the resulting endpoint detection determination may only be valid for a very short number of runs before process drift and noise render them ineffective. Only recently have researchers begun to examine methods to automatically select and weight spectral channels for estimation and diagnosis of process behavior. This paper will explore the use of principal component analysis (PCA)-based T/sup 2/ formulation to filter out noisy spectral channels and characterize spectral variation of optical emission spectroscopy (OES) correlated with endpoint. This approach is applied and demonstrated for patterned contact and via etching using digital semiconductor's CMOS6 (0.35-/spl mu/m) production process.

An empirical three-dimensional crossover capacitance model for multilevel interconnect VLSI circuits

Abstract: We develop an empirical model for the crossover capacitance induced by the wire crossings in VLSI with multilevel metal interconnects. The crossover capacitance, which is formed in any three adjacent layers and of a three-dimensional (3-D) nature, is derived in closed form as a function of the wire geometry parameters. The total capacitance on a wire passing many crossings can then be easily determined by combining the crossover capacitance with the two-dimensional (2-D) intralayer coupling capacitance defined on a same layer. The model agrees well with the numerical field solver (with a 6.7% root-mean-square error) and measurement data (with a maximum error of 4.17%) for wire width and spacing down to 0.16 /spl mu/m and wire thickness down to 0.15 /spl mu/m. The model is useful for VLSI design and process optimization.

The mask error factor in optical lithography

Abstract: The primary cause of greater than unity mask error factor (MEF) is degradation of image integrity. Mathematical description of image formation reveals the gradual loss of image shape control by photomask features as the critical dimension decreases below 0.8(/spl lambda//NA). The growing contribution of mask critical dimension error to line-width variation prompts generalization of the conventional two-dimensional (2-D) exposure-defocus window (ED window) to a three-dimensional (3-D) mask-exposure-defocus volume (ED volume), adding mask tolerance to exposure latitude and depth-of-focus as the important parameters of a process. The increase in MEF with feature nesting means that the relative importance of sources of line-width variation changes with pattern pitch. Mask improvement is the most effective means to reduce line-width variation for dense features, but lens quality is the most significant factor affecting line-width control for sparse patterns. The approximately 20% higher MEF of dark-field masks, low MEF of alternating phase-shifting masks, and relatively high MEF of assist features all have ramifications on lithography strategies for printing sparse lines. The MEF does not simply indicate a need for high-quality masks, it also sheds light on the critical areas in which improvements are needed for successful lithography, and the disciplines that need to cooperate for successful device fabrication.

A methodology for product mix planning in semiconductor foundry manufacturing

Abstract: Since a semiconductor foundry plant manufactures a wide range of memory and logic products using the make-to-order business model, the product mix is an important production decision. This paper first describes the characteristics of the product mix planning problem in foundry manufacturing that are attributable to the long flow time and queuing network behaviors. The issues of time bucket selection, mix optimization and bottleneck-based planning are next addressed. A decision software system based on integer linear programming techniques and a heuristic procedure has been implemented for mix planning. Data provided by a wafer plant has been used to study problems related to product mix planning. It was determined that the suitable time bucket of planning is either one week or one month and the lead-time offset factor should be included in the logic of workload calculation. This paper also presents various facets of product mix decisions and how they should be integrated with operations management.

Improved method for the oxide thickness extraction in MOS structures with ultrathin gate dielectrics

Abstract: An improved method for the assessment of the oxide thickness applicable to advanced CMOS technologies is proposed. To this end, a proper combination of Maserjian's technique and of Vincent's method is used to alleviate the unknown parameter inherent to both extraction procedures and which depends on the employed carrier statistics. The new method has been successfully applied to various technologies with gate oxide thickness ranging from 7 nm to 1.8 nm.

Effect of parameter variations at chip and wafer level on clock skews

Abstract: In this paper, a methodology is proposed to determine clock skews and the performance of clock architectures considering parameter variations in an early stage of technology development. With this methodology, it is possible to separate process-induced clock skew from other effects like imperfect loading. Parameter variations are seen as one of the most important effects influencing chip performance in future. By comparing a 0.45- and a 0.25-/spl mu/m technology, it is shown that in the future, process variations will increase clock skew. The clock skews are determined by measuring the relevant device and metal line parameters as a function of position over chip and wafer. In the past, parameters like IDS, Vth, and resistances could be measured very precisely, although it was difficult to measure low capacitances of single metal lines in the range of femto farad. Thus a new measurement method is used to determine interconnect capacitances extremely precisely. Based on these measurement data, a netlist of a defined clock tree is created by a C-program, and the clock signal delay is simulated. From the delay simulation, we calculate the clock skew for each chip dependent on the parameter variations. Experimental results are separated into a basic random fluctuation part and processing-related contributions on the chip and wafer levels. In addition, the effect of temperature gradients on each chip to the clock skew is simulated. The methodology presented is not restricted to just one clocktree but allows investigation of all kinds of clock distribution circuits. The method has clear advantages with respect to chip area against clocktree realizations on a testchip. No direct and costly measurement of signal delays by voltage contrast methods is required, since all parameters are determined by measurement on the device level.

An efficient photoresist development simulator based on cellular automata with experimental verification

Abstract: An efficient and practical photoresist development simulator based on cellular automata is presented. Image reversal and chemical amplification processes are also simulated using this simulator. To verify the simulator, a series of experiments have been designed and performed using the Shipley SNR-248 negative resist, a stepper, and a deep ultraviolet source at 248 nm. Experiments were performed for periodic and isolated lines with pitches 300, 400, 500, and 1000 nm, for exposure energy doses of 11, 13, 17, and 23 mJ/cm/sup 2/, and with developer temperatures of 0, 20, and 80/spl deg/C. In all cases, the simulator results were found to be in very good agreement with the corresponding experimental results. The simulator has also successfully reproduced the incomplete opening effect observed in the case of close-spaced parallel lines.

Device dependent control of chemical-mechanical polishing of dielectric films

Abstract: This paper presents a control scheme for run-to-run control of chemical-mechanical polishing (CMP). The control scheme tracks both device pattern dependent and equipment induced disturbances. The structure of the controller is such that sensitivity to qual (unpatterned blanket oxide) wafer frequency is minimized. Additionally, prethickness variation and metrology delay are accounted for in the design. Results from applying this scheme in volume production are presented.

Optimal predictive control with constraints for the processing of semiconductor wafers on bake plates

Abstract: An optimal control scheme is designed to improve repeatability by minimizing the loading effects induced by the common processing condition of placement of a semiconductor wafer at ambient temperature on a large thermal-mass bake plate at processing temperature. The optimal control strategy is a model-based method using linear programming to minimize the worst-case deviation from a nominal temperature set point during the load disturbance condition. This results in a predictive controller that performs a predetermined heating sequence prior to the arrival of the wafer as part of the resulting feedforward/feedback strategy to eliminate the load disturbance. This procedure is based on an empirical model generated from data obtained during closed-loop operation. It is easy to design and implement for conventional thermal processing equipment. Experimental results are performed for a commercial conventional bake plate and depict an order-of-magnitude improvement in the settling time and the integral-square temperature error between the optimal predictive controller and a feedback controller for a typical load disturbance.

Evaluating the impact of process changes on cluster tool performance

Abstract: Cluster tools are highly integrated machines that can perform a sequence of semiconductor manufacturing processes. Their integrated nature can complicate analysis when evaluating how process changes affect the overall tool performance. This paper presents two integrated models for understanding the behavior of a simple, single loadlock cluster tool. The first model is a network model that evaluates the total lot processing time for a given sequence of activities. By including a manufacturing process model (in the form of a response surface model, or RSM), the model calculates the lot makespan, the total time to process a lot of wafers, as a function of the process parameter values and other operation times. This model allows us to quantify the sensitivity of total lot processing time with respect to process parameters and times. In addition, we present an integrated simulation model that includes a process model. For a given scheduling rule that the cluster tool uses to sequence wafer movements, we can use the simulation to evaluate the impact of process changes, including changes to product characteristics and changes to process parameter values. In addition, we can construct an integrated network model to quantify the sensitivity of total lot processing time with respect to process times and process parameters in a specific scenario. We also present an evaluation of the effectiveness of two different scheduling rules, push and pull. The examples presented here illustrate the types of insights that we can gain from using such methods. Namely, the lot makespan is a function not simply of each operation's process time, but specifically of the chosen process parameter values. Modifying the process parameter values may also have significant impacts on the manufacturing system performance, a consequence of importance that is not readily obvious to a process engineer when tuning a process. This result can be seen either with the decrease of raw process time causing little change to the makespan, or the extreme example in which this could cause an increase in makespan because of an inefficient scheduling rule. Additionally, because the cluster tool's maximum throughput, which is the inverse of the lot makespan, depends on the process parameters, the tradeoffs between process performance and throughput should be considered when evaluating potential process changes and their manufacturing impact.

Reducing airborne molecular contamination by efficient purging of FOUPs for 300-mm wafers-the influence of materials properties

Abstract: The control of airborne molecular contamination (AMC) plays an increasing role in semiconductor manufacturing processes. A method to reduce AMC is purging of wafer boxes with inert gas. In this study, data on the practicability and optimization of purging a front opening unified pod (FOUP), a wafer box for 300-mm wafers, are presented. Different parameters for the purge process are evaluated experimentally. Key values for the assessment of efficiency are the time-dependent content of oxygen and humidity in the FOUP. The increase in the key values after the purge was measured and the construction of the FOUP was modified in order to obtain sufficient tightness. Spatially resolved measurements reveal the homogeneity of the purge. Experimental data are compared to data obtained by a simulation using a computational fluid dynamics program. Values for oxygen are in agreement with the calculated curves. In contrast to this, an additional, long-lasting contribution that was not taken into account in the simulations makes depletion of humidity slower than expected. This contribution is explained with the desorption and permeation of humidity through the plastic walls of the FOUP. The presence of both effects, desorption and permeation, is proved and quantified. Materials properties turn out to heavily affect purge effectiveness and the postpurge ingress of certain contaminants in a wafer box.

An analytical model of multiple ILD thickness variation induced by interaction of layout pattern and CMP process

Abstract: In this paper, an analytical model for chemical mechanical polishing (CMP) is described. This model relates the physical parameters of the CMP process to the in-die variation of interlayer dielectric (ILD) in multilevel metal processes. The physical parameters considered in this model include the deposited ILD profile, deformation of the polishing pad and the hydrodynamic pressure of slurry flow. Model parameters are adjusted based on the first ILD layer and then applied to the upper ILD layers. Comparison of simulated results with sample data is performed at the die level of a state-of-the-art microprocessor.

Real-time control of reactive ion etching using neural networks

Abstract: This paper explores the use of neural networks for real-time, model-based feedback control of reactive ion etching (RIE). This objective is accomplished in part by constructing a predictive model for the system that can be approximately inverted to achieve the desired control. An indirect adaptive control (IAC) strategy is pursued. The IAC structure includes a controller and plant emulator, which are implemented as two separate back-propagation neural networks. These components facilitate nonlinear system identification and control, respectively. The neural network controller is applied to controlling the etch rate of a GaAs/AlGaAs metal-semiconductor-metal (MSM) structure in a BCl/sub 3//Cl/sub 2/ plasma using a Plasma Therm 700 SLR series RIE system. Results indicate that in the presence of disturbances and shifts in RIE performance, the IAC neural controller is able to adjust the recipe to match the etch rate to that of the target value in less than 5 s. These results are shown to be superior to those of a more conventional control scheme using the linear quadratic Gaussian method with loop-transfer recovery, which is based on a linearized transfer function model of the RIE system.

A thermal van der Pauw test structure

Abstract: A micromachined thermal van der Pauw test structure is reported. Similar in principle to the conventional electrical van der Pauw Greek cross test structures, it enables the in-plane thermal sheet conductivities of thin films to be determined. The microstructure was fabricated using a commercial CMOS application-specific integrated circuit process followed by anisotropic silicon etching. It consists of a cross-shaped sandwich of the dielectric CMOS layers isolated from the bulk silicon by four narrow suspension arms. Integrated polysilicon resistors make it possible to generate controlled amounts of heat power and to measure local temperature changes to determine the thermal response of the structure. The measurement principle exploits the analogy between the two-dimensional (2-D) heat flow in thin film samples and the electrical current pattern in thin film conductors. A thermal sheet resistance of 1.87/spl times/10/sup 5/ K/W was extracted from the complete sandwich of the dielectric CMOS layers. This resistance is equivalent to an average in-plane thermal conductivity of the dielectric layer sandwich of /spl kappa/=1.44 W m/sup -1/ K/sup -1/. Thermal finite element simulations showed that the radiative heat loss from the structure has a negligible effect on the extracted /spl kappa/ value.

Using neural networks to construct models of the molecular beam epitaxy process

Abstract: This paper presents the systematic characterization of the molecular beam epitaxy (MBE) process to quantitatively model the effects of process conditions on film qualities. A five-layer, undoped AlGaAs and InGaAs single quantum well structure grown on a GaAs substrate is designed and fabricated. Six input factors (time and temperature for oxide removal, substrate temperatures for AlGaAs and InGaAs layer growth, beam equivalent pressure of the As source and quantum well interrupt time) are examined by means of a fractional factorial experiment. Defect density, X-ray diffraction, and photoluminescence are characterized by a static response model developed by training back-propagation neural networks. In addition, two novel approaches for characterized reflection high-energy electron diffraction (RHEED) signals used in the real-time monitoring of MBE are developed. In the first technique, principal component analysis is used to reduce the dimensionality of the RHEED data set, and the reduced RHEED data set is used to train neural nets to model the process responses. A second technique uses neural nets to model RHEED intensity signals as time series, and matches specific RHEED patterns to ambient process conditions. In each case, the neural process models exhibit good agreement with experimental results.

Segment-based approach for real-time reactive rescheduling for automatic manufacturing control

Abstract: We propose a new segment-based approach for a real-time reactive rescheduling method. The approach is applicable to actual large-scale manufacturing systems, such as fully automated semiconductor wafer fabrication lines. The proposed method can efficiently (in terms of computation time) schedule processing operations at equipment units by dividing a wide scheduling range into small segments and by using a greedy scheduling algorithm. It can also reactivate infeasible schedules without sacrificing the quality of schedules in terms of productivity as much as possible. From the simulation results obtained, we experimentally confirmed that the proposed method reactivates, without significant productivity loss caused by the rescheduling algorithm itself, infeasible schedules faster than a comparative method commonly in use today. Consequently, the proposed method manages to keep schedules at each equipment unit executable in terms of processing performance and schedule quality.

Wafer thermal desorption spectrometry in a rapid thermal processor using atmospheric pressure ionization mass spectrometry

Abstract: This paper demonstrates the possibility of performing thermal desorption spectrometry (TDS) on wafers in an atmospheric pressure rapid thermal processor (RTP). A special gas sampling system is described, which allows the analysis of gas composition inside the RTP chamber with atmospheric pressure ionization mass spectrometry (APIMS). Sampling is controlled with no valve operation and high dilution of the sample gas flow can be achieved while maintaining a short sample transfer time. It is shown how gas flows can be optimized to improve the sensitivity and resolution of TDS spectra. The RTP-APIMS setup was used in a study of H/sub 2/O absorption by low dielectric constant fluorinated silica glass (FSG) films, helping to develop a cap that reduced H/sub 2/O absorption upon storage by a factor of 60. NH/sub 3/ is shown to desorb from FSG and SiO/sub 2/ films deposited by plasma-enhanced chemical vapor deposition (PECVD), which may be of concern for the reliability of integrated circuits.

SHEWMA: an end-of-line SPC scheme using wafer acceptance test data

Abstract: In this paper, an end-of-line quality control scheme based on wafer acceptance test (WAT) data is presented. Due to the multiple-stream and sequence-disorder effects typically present in the WAT data, an abnormal process shift caused by one machine at an in-line step may become vague for detection using end-of-line WAT data. A methodology for generating robust design parameters for the simultaneous application of Shewhart and EWMA control charts to WAT data is proposed. This SHEWMA scheme is implemented in a foundry environment and its detection and diagnosis-enhancing capabilities are validated using both numerical derivations and fab data. Results show that the SHEWMA scheme is superior to the current practices in detection speed. Its use is complementary to the existing in-line SPC for process integration.

Analysis of laser metal-cut energy process window

Abstract: Metal fuses for laser redundant links have been used for years in laser repair application. Nonetheless, reliability problems have occurred for laser metal cut structures, such as the material leftover remaining at the bottom of the cut site or the formation of a lower corner crack. In this paper, a special finite element Two-Stage Laser Cut Simulation Model (TSLCSM) is proposed to study the cut process. Compared with other simulation methods for similar purposes, the proposed model not only includes the stress-relief effect caused by cracking and breakthrough of passivation caused by upper corner cracks, but it also explains the laser-cut mechanism ignoring the metal underlayer. It proves earlier experimental results that a laser-energy window exists for each cut structure under a specified laser pulse. Different laser cut structures and different laser parameters are considered in the simulation, and useful guidelines are obtained for a maximum laser-energy process window. Experimental observations consistent with simulation results show that the differential between upper corner stress and lower corner stress is temporarily dependent on the passivation breakthrough caused by upper corner cracks. Also, it is shown that lower corner cracks can be formed at much lower laser energies than previously expected.

Neurofuzzy modeling of chemical vapor deposition processes

Abstract: The modeling of semiconductor manufacturing processes has been the subject of intensive research efforts for years. Physical-based (first-principle) models have been shown to be difficult to develop for processes such as plasma etching and plasma deposition, which exhibit highly nonlinear and complex multidimensional relationships between input and output process variables. As a result, many researchers have turned to empirical techniques to model many semiconductor processes. This paper presents a neurofuzzy approach as a general tool for modeling chemical vapor deposition (CVD) processes. A five-layer feedforward neural network is proposed to model the input-output relationships of a plasma-enhanced CVD deposition of a SiN film. The proposed five-layer network is constructed from a set of input-output training data using unsupervised and supervised neural learning techniques. Product space data clustering is used to perform the partitioning of the input and output spaces. Fuzzy logic rules that describe the input-output relationships are then determined using competitive learning algorithms. Finally, the fuzzy membership functions of the input and output variables are optimally adjusted using the backpropagation learning algorithm. A salient feature of the proposed neurofuzzy network is that after the training process, the internal units are transparent to the user, and the input-output relationship of the CVD process can be described linguistically in terms of IF-THEN fuzzy rules. Computer simulations are conducted to verify the validity and the performance of the proposed neurofuzzy network for modeling CVD processes.

A high-density, matched hexagonal transistor structure in standard CMOS technology for high-speed applications

Abstract: In this paper, a very dense CMOS hexagonal transistor structure is presented. The main advantages of the transistors are the low parasitic drain and source capacitance caused by the small area. The matching properties of this structure have been investigated, and these results have been compared with those for traditional finger-style structures. Exploiting the advantages, these transistors are very well suited for high-speed applications with a demand for both good matching and a small area, such as multibit current steering D/A converters or wireless applications. The test chips have been implemented in a standard 0.5-/spl mu/m CMOS technology. No adaptations to the standard technology have been made to realize the structures.

Thermal uniformity of 12-in silicon wafer during rapid thermal processing by inverse heat transfer method

Abstract: Through an inverse heat transfer method, this paper presents a finite difference formulation for determination of incident heat fluxes to achieve thermal uniformity in a 12-in silicon wafer during rapid thermal processing. A one-dimensional thermal model and temperature-dependent thermal properties of a silicon wafer are adopted in this study. Our results show that the thermal nonuniformity can he reduced considerably if the incident heat fluxes on the wafer are dynamically controlled according to the inverse-method results. An effect of successive temperature measurement errors on thermal uniformity is discussed. The resulting maximum temperature differences are only 0.618, 0.776, 0.981, and 0.326/spl deg/C for 4-, 6-, 8- and 12-in wafers, respectively. The required edge heating compensation ratio for thermal uniformity in 4-, 6-, 8and 12-in silicon wafers is also evaluated.