Showing papers in "Technical report of IEICE. VLD in 2007"
Journal Article•
2 citations
TL;DR: A system consisting of a full-3D process simulator for stress calculation and k · p band calculation that takes into account the subband structure that is a powerful tool to optimize device structures with all stress components.
Abstract: We have developed a system consisting of a full-3D process simulator for stress calculation and k · p band calculation that takes into account the subband structure. Our simulations are in good agreement with the experimental data of strained Si-pMOSFETs of 65nm technology devices. This system is a powerful tool to optimize device structures with all stress components.
Journal Article•
TL;DR: An on-chip bus architecture for post-fabrication timing calibration is proposed and the proposed architecture reduces the transistor size and increases the interconnect delay increase.
Abstract: As the transistor size shrinks, the horizontal coupling capacitance between adjacent wires becomes dominant for wire load. Especially for an on-chip bus, since each line of a bus runs in parallel for a long distance, inter-wire coupling capacitance is larger than other interconnects. An interconnect delay increase caused by inter-wire coupling capacitance increase. Also, as the transistor size shrinks, process variations increase. With process variations, delay variations cause the yield loss. In this paper, we propose an on-chip bus architecture for post-fabrication timing calibration.