Patent
A sense amplifier with an integral logic function
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TLDR
A sense amplifier with an integral logic function for use in a circuit such as a tag cache portion of a microprocessor cache is presented in this paper, where an exclusive-OR function is performed between the logic state of the sensed bit and a corresponding input address bit.Abstract:
A sense amplifier with an integral logic function for use in a circuit such as a tag cache portion of a microprocessor cache. In one form, the integral logic function is an exclusive-OR function. The sense amplifier senses a differential voltage developed between a differential pair of bit lines which are coupled to predetermined bit positions of a plurality of entries in a tag cache. While sensing the voltage, an exclusive-OR function is performed between the logic state of the sensed bit and a corresponding input address bit. If the input address bit matches the sensed bit, then a match signal is asserted. The value of the corresponding input address bit configures the circuit either to provide an output signal in a predetermined logic state if a true bit line signal voltage exceeds a complement bit line signal voltage, or to provide the output signal in the predetermined state if the complement bit line signal voltage exceeds the true bit line signal voltage.read more
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References
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Patent
Dynamic sense amplifier for CMOS static RAM
TL;DR: In this article, a sense amplifier for use in a CMOS static random access memory is proposed, which consists of two sensing transistors with their sources coupled to a common pull down node, a pull down transistor for drawing current from the pulldown node during sensing operations, and a four transistor latch coupled to the drains of the two transistors, typically latching in less than two nanoseconds.
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TL;DR: In this article, a single-ended sense amplifier with regenerative feedback is proposed for fast and reliable sensing of a small voltage differential, which is accomplished by the integration of a latch.
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Takashi Obara,Shouji Kaneko +1 more
TL;DR: In this article, a sense amplifier circuit comprising a balancing circuit capable of establishing an electrical path between not only the sense nodes but also the control nodes which are operable to control transistors provided between the senses and a voltage supply to apply the supply voltage level to one sense node and remain low level on the other sense node for preparation of reading out of accessed information is provided.
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