Journal ArticleDOI
Analytical Modeling of Deterministic Jitter in CMOS Inverters
A. K. Verma,Jai Narayan Tripathi +1 more
- Vol. 2, pp 64-73
TLDR
In this paper , an analytical approach is presented which estimates jitter in CMOS inverters in the presence of power supply noise (PSN), data noise (DN), and ground-bounce noise (GBN) by deriving analytical relationships.Abstract:
With the advancement of semiconductor technology (enabling the dimensions of the switching devices in the range of nanometer scale) designing, modeling, and optimization of high-speed circuits are becoming very complicated. Various issues related to signal and power integrity come into picture at high-frequency operations, e.g., jitter, cross-talk, electromagnetic interference, etc. In this article, an analysis of the CMOS inverter in presence of deterministic noise is presented. An analytical approach is presented which estimates jitter in CMOS inverters in the presence of power supply noise (PSN), data noise (DN), and ground-bounce noise (GBN) by deriving analytical relationships. The proposed analytical method takes into account the device parameters to model timing uncertainty. The expression for jitter is obtained by estimating the deviation of each transition edge from its ideal position. Several examples (simulations as well as measurement) are presented to validate the proposed modeling. These examples include comparing the analytical results with the simulation results obtained using an SPICE-based simulator as well as doing the same with the experimental results using two different CMOS inverter integrated circuits (ICs). In order to test the independence of the proposed modeling approach on a specific technology node, the results are verified by considering different technology nodes such as: 40 nm, 65 nm, and 180 nm from United Microelectronics Corporation. Also, two different ICs (M74HC04, and MC74AC04 N) from different vendors are used for measurement. The results obtained using the proposed methodology are in close consonance with those obtained from simulations using the SPICE-based simulator and the experiments.read more
Citations
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Variability-Aware Modeling of Supply Induced Jitter in CMOS Inverters
A. K. Verma,Jai Narayan Tripathi +1 more
TL;DR: In this article, the impact of variability on power supply-induced jitter in integrated circuits is discussed and an analytical approach is presented to model timing uncertainty in the output response of CMOS inverters due to process variations as well as power supply noise.
References
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