Proceedings ArticleDOI
Application and analysis of IDDQ diagnostic software
Phillip J. Nigh,Donato O. Forlenza,Franco Motika +2 more
- pp 319-327
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TLDR
A methodology for performing defect localization based upon IDDq test information (only) is presented, which supports multiple fault models and has been successfully applied to a large number of samples-including ones that have been verified through failure analysis.Abstract:
A current disadvantage of IDDq testing is lack of software-based diagnostic tools that enable IC vendors to create a large database of defects uniquely detected with this test method. We present a methodology for performing defect localization based upon IDDq test information (only). Using this technique, fault localization can be completed within minutes (e.g. <5 minutes) after IC testing is complete. This technique supports multiple fault models and has been successfully applied to a large number of samples-including ones that have been verified through failure analysis. Data is presented related to key issues such as diagnostic resolution, hardware-to-fault model correlation, diagnostic current thresholds, and the diagnosability of various defect types.read more
Citations
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Proceedings ArticleDOI
Intrinsic leakage in low power deep submicron CMOS ICs
TL;DR: Transistor intrinsic leakage reduction as functions of bias point, temperature, source-well backbiasing, and lowered power supply (V/sub DD/) are reported.
Proceedings ArticleDOI
Current signatures: application
Anne Gattiker,Wojciech Maly +1 more
TL;DR: This paper is a first step toward current signature step detection in a noisy test environment and application of current signatures in die selection and defect diagnosis.
Proceedings ArticleDOI
A persistent diagnostic technique for unstable defects
TL;DR: A technique using the layout information for an open fault diagnosis, and a testing method for the delay fault are discussed, and some experimental results of actual chips are shown.
Proceedings ArticleDOI
Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment
Phillip J. Nigh,David P. Vallett,A. Patel,J. Wright,Franco Motika,Donato O. Forlenza,R. Kurtulik,W. Chong +7 more
TL;DR: The testing, reliability stressing, characterization, fault diagnosis and physical analysis results are presented for 25 devices including "IDDq-only" failures and "delay test- only" failures.
Journal ArticleDOI
IDDX-based test methods: A survey
S.S. Sabade,Duncan M. Walker +1 more
TL;DR: A survey of the research reported in the literature to extend the use of IDDX tests to deep sub-micron (DSM) technologies is presented.
References
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Proceedings ArticleDOI
Defect classes-an overdue paradigm for CMOS IC testing
TL;DR: In this paper, the authors propose a comprehensive test paradigm for testing CMOS ICs that uses defect classes based on measured defect electrical properties, and describe test pattern requirements for each defect class and propose a test paradigm.
Proceedings ArticleDOI
CMOS bridging fault detection
T.M. Storey,Wojciech Maly +1 more
TL;DR: It is shown that stuck fault test generation, while inherently incapable of directly expressing many of the likely CMOS faults, was still able to generate a set of effective test patterns, and current testing produced test patterns that were consistently more effective in detecting bridging faults.
Proceedings ArticleDOI
Test generation for current testing
P. Nigh,Wojciech Maly +1 more
TL;DR: In this article, the concept of current testing is described; the classes of defects detectable by current testing and the conditions to detect a given defect are described; and a general test-vector generation algorithm for current testing was developed and applied to two examples.
Proceedings ArticleDOI
Test Pattern Generation for Realistic Bridge Faults in CMOS ICs
F.J. Ferguson,T. Larrabee +1 more
TL;DR: This paper simulates complete single stuck-at test sets against a low-level model of bridge defects showing that an unacceptably high percentage of such defects are not detected by the complete stuck- at test sets.