Patent
Binary coded decimal correction apparatus for use in an arithmetic unit of a data processing unit
Virendra S. Negi,Arthur Peters +1 more
TLDR
In this paper, a binary arithmetic logic unit can be corrected to provide a binary coded decimal result by use of correction logic which is responsive to the result produced by the BALU, the type of operation being performed, and whether the binary ALU produced a carry as a result of its arithmetic operation on such operands.Abstract:
Binary coded decimal operands may be operated on by use of a binary arithmetic logic unit and the result corrected to provide a binary coded decimal result by use of correction logic which is responsive to the result produced by the binary arithmetic logic unit, the type of operation being performed and whether the binary arithmetic logic unit produced a carry as a result of its arithmetic operation on such operands.read more
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Patent
Microcomputer system for digital signal processing
TL;DR: In this article, a real-time digital signal processing (RLD) system was proposed, which employs a single-chip microcomputer device (10) having separate on-chip program ROM (14) and data RAM (15), with separate address and data paths for program and data.
Patent
Fast BCD/binary adder
TL;DR: In this paper, a fast BCD/Binary Adder is proposed for selectively performing either binary or BCD arithmetic operations using an approach in which, for BCD addition, an appropriate correction value is always caused to be added to one of the input operands and an appropriate corrected value conditionally subtracted from the result where required to give a proper BCD result.
Patent
Digital adder circuit for binary-coded numbers of radix other than a power of two
TL;DR: In this article, a digital adder circuit for binary-coded-decimal operation, comprising a set of multiplexers (11) conditioned with a pattern of input bits causing them to form an intermediate result (IR) equal to the sum of the two operands (A0-A3, B0-B3) plus a correction value of six.
Patent
Bit sliced decimal adding/subtracting unit for multi-digit decimal addition and subtraction
TL;DR: In this article, the offset data generator has first and second logical gates, and the output signal from the first logical gate is used for the first four bits of the first 4-bit offset data.
Patent
Binary-to-BCD conversion
Sanu Mathew,Ram Krishnamurthy +1 more
TL;DR: In this paper, various embodiments of circuitry and methods to convert from a binary value to a BCD value are discussed, as well as methods for converting from binary values to BCD values.
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Patent
Arithmetic unit for a digital data processor
TL;DR: In this article, a digital arithmetic unit for adding and subtracting multidigit binary coded decimal numbers having a zoned format is presented, which is done by means of a parallel binary adder of a type suitable for handling pure binary numbers and having no special provisions for accommodating zoned decimal numbers.
Patent
Current mode binary/bcd arithmetic array
TL;DR: In this article, an arithmetic logic array employing soft-saturating current mode logic gates operates on pure binary data or binary coded decimal data, and two 4-bit data inputs are received along with a 5-bit Op code, a carry input, and decimal arithmetic operation signals.
Patent
Time calculator with mixed radix serial adder/subtraction
Mitsuhiro Goto,Katsumi Yamamura +1 more
TL;DR: In this paper, the first and second calculators are adapted to receive and add or subtract two time figures and produce a result, and the second calculator is adapted to combine this result with a further figure.
Patent
Electronic calculator or microprocessor having a hexadecimal/binary coded decimal arithmetic unit
TL;DR: In this paper, an electronic calculator or microprocessor system of the type with keyboard input and a visual display is implemented with a semiconductor chip having a hexadecimal/binary coded decimal format arithmetic unit for performing arithmetic operations on numeric data inputted by the keyboard further.