Patent
Bus selection control in a data transmission apparatus for a multiprocessor system
Yasushi Fukunaga,Tadaaki Bandoh,Ryosei Hiraoka,Hidekazu Matsumoto,Jushi Ide,Tetsuya Kawakami +5 more
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TLDR
In this article, a data transmission apparatus is provided for each of the main memory and the processors and includes bus request control lines for transferring bus request signals and bus control signals, and a bus controller for separately controlling selections of the address bus, the data bus and the answer bus in response to the signals on the bus control lines and the request signal.Abstract:
In a multiprocessor system having a main memory and a plurality of processors connected through common address bus, data bus and answer bus for data transfer, a data transmission apparatus is provided for each of the main memory and the processors and includes bus request control lines for transferring bus request signals and bus control signals, and a bus controller for separately controlling selections of the address bus, the data bus and the answer bus in response to the signals on the bus request control lines and the request signal. Overlapped processing such as data write and data write answer or data read and data read answer in one cycle is possible.read more
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References
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Patent
Cache storage line shareability control for a multiprocessor system
TL;DR: In this paper, a multiprocessor (MP) system is described having central processors (CPs) in which each CP has a store-in-cache (SIC) with an associated processor directory (PD).
Patent
Data processing system
TL;DR: In this paper, a bus control unit is provided for delivering a "who" signal (which is used for detecting a requesting unit) to the first one of said serially connected data processing units when said unit requests the use of said bus assembly.
Patent
Computer system with a memory access arbitrator
TL;DR: In this article, an access arbitrator couples the access acknowledge signal to one of the memory utilization devices issuing an access request signal and disables another memory utilization device to issue the address transfer and read/write control information on the two bus control lines.
Patent
Bus for a data processing system with overlapped sequences
TL;DR: In this paper, a digital data processing system including an interconnection for the various elements that constitute the system is described, where each element that connects to the interconnection is called a nexus.
Patent
Multiprocessor computer systems
TL;DR: In this article, a fault channel is accessed by another processor of the system, enabling the operation of the former processor to be monitored by the latter by using the control console of a conventional computer.