Patent
Clock generator which generates a non-overlap clock having fixed pulse width and changeable frequency
Hiroyuki Kawai,Shinichi Nakagawa +1 more
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TLDR
In this paper, a clock generator is cascade connected with a plurality of single-phase pulse generator circuits including RS flip-flops and delay circuits for defining the pulse width of one output at the RS flipflop through gates controlling propagation of the other output of the RS flipsflop, and the final clock frequency is variable by switching control of each gate.Abstract:
A clock generator which is cascade connected a plurality of single-phase pulse generator circuits including RS flip-flops and delay circuits for defining the pulse width of one output at the RS flip-flop through gates controlling propagation of the other output of the RS flip-flop, so that the final clock frequency is variable by switching control of each gate, whereby a pulse width of each single-phase clock is defined by a delay duration of a delay circuit, thereby not depending on wave forms of the external clock and also the gates connected between the respective single-phase pulse generating circuits are switching-controlled to enable the frequency of the output clock to be variable.read more
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High speed serial link for fully duplexed data communication
TL;DR: In this article, a system for converting between parallel data and serial data is described, where individual bits of the parallel data (12) are latched into individual registers (117) and each register is coupled to a corresponding AND gate (110) which is also connected to receive phased clock signals.
Patent
Driving device of charge pump circuit and driving pulse generation method thereof
TL;DR: In this article, a semiconductor circuit device includes an oscillator for outputting an oscillating signal, a driving signal generator for generating driving signals having respective phases based on a counting of oscillations of the oscillating signals, and a charge pump circuit driven by the driving signals.
Patent
Clock multiplier using nonoverlapping clock pulses for waveform generation
Andrew Brown,Nicholas P. Mati +1 more
TL;DR: In this paper, an improved clock generator performs clock multiplication using selectable generation of clock edges, where the clock multiplier divides an input clock period into N edges by generating N non-overlapping clock pulses synchronized to the period of the reference clock.
Patent
Clock generator for providing a pair of nonoverlapping clock signals with adjustable skew
TL;DR: In this article, a flip-flop state machine is used to clock a pair of complementary switches that direct successive pulses of a clock signal alternately to one and then the other of output clock signal ports.
Patent
Multiple-phase clock signal generator for integrated circuits, comprising PLL, counter, and logic circuits
TL;DR: In this article, a phase-locked loop (PLL) is used to generate a clock signal having a particular phase, at the output of each combinational logic gate, which can be used to produce different combinations of the outputs of the counter.
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Patent
Phase synchronization circuit
Haruhiko Nakamura,Junya Tempaku +1 more
TL;DR: A phase synchronization circuit for controlling a graphic display device in a teletext receiving system was proposed in this paper, which includes a delay circuit, adapted to delay in sequence clock signals which are to be phase-synchronized with a reference signal and to produce in sequence delayed clock signals, and a selection circuit, including set/reset circuits and gates.
Patent
Apparatus for synchronization of a first signal with a second signal
Craig Clapp,Neil R. Adams +1 more
TL;DR: In this paper, a mechanism for synchronizing a first signal with a second signal comprising a plurality of delay means is presented. But it is not shown how to synchronize the two signals at the same time.
Patent
System clock generator in integrated circuit
TL;DR: In this paper, a system clock generator for use in a CMOS LSI chip includes a clock control signal generator for developing a control signal in response to a clock generating instruction or inhibition instruction.
Patent
Arrangement for synchronizing the phase of a local clock signal with an input signal
TL;DR: In this article, the phase synchronization of a locally generated clock signal with the phase of an input signal is usually effected by using a phase-locked loop, but this has a drawback that a certain run-in time is necessary to be sure that the clock signal is stable.
Patent
Multiple phase clock generator
TL;DR: In this paper, a two phase clock signal with separation between the two phases is produced from a single phase clock, and two complementary input signals are derived from the single-phase clock and are transferred by separate transfer gates to individual push/pull amplifiers.