Patent
Co-packaged MOS-gated device and control integrated circuit
Roberto Martinez,Chuan Cheah +1 more
TLDR
In this article, a power transistor die has a lower surface and an upper surface, and a control circuit for controlling the power transistor is mounted to the upper surface of the die using an insulating epoxy.Abstract:
An electronic package for an electronic device includes a substrate. A power transistor die has a lower surface and a upper surface, and the lower surface of the power transistor die is mounted on the substrate. A control circuit for controlling the power transistor is mounted to the upper surface of the power transistor die using an insulating epoxy.read more
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Patent
Semiconductor bilateral switch
Steven Sapp,David S. Schoenwald +1 more
TL;DR: In this article, a semiconductor bilateral switch that minimizes the on-state resistance by making a common-source connection between the switch transistors internal to the package is presented.
Patent
Integrated circuit package for semiconductor devices with improved electric resistance and inductance
TL;DR: A semiconductor integrated circuit (SIC) is a MOSFET with a lead-frame pad and a bonding metal area that is disposed over at least two adjacent sides of the die as mentioned in this paper.
Patent
Semiconductor package including two semiconductor die disposed within a common clip
TL;DR: A co-package semiconductor device including an outer clip in the form of a metal can includes also two semiconductor dies, at least one of which uses the outer clip as an electrical connector.
Patent
Semiconductor device package with plural pad lead frame
Glyn Connah,Peter R. Ewer +1 more
TL;DR: In this paper, a semiconductor device package has a lead frame with four or more die receiving pads, and the die and pads are enclosed by a molded plastic housing and short sections of the pads protrude through the housing wall.
Patent
Hybrid package including a power MOSFET die and a control and protection circuit die with a smaller sense MOSFET
TL;DR: In this article, a power MOSFET and a logic and protection circuit die are mounted on a common lead frame pad, such as a TO220 lead-frame pad.
References
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Patent
Semiconductor integrated circuit device capable of surely electrically insulating two semiconductor chips from each other and fabricating method thereof
TL;DR: In this paper, the authors provided a semiconductor integrated circuit device having integrally a flat-plate-shaped die pad 11 formed in a lead frame 10, a first semiconductor chip 7 bonded via a first adhesive layer 1.
Patent
Face on face flip chip integration
Robert Payne,Herbert Reiter +1 more
TL;DR: In this article, a logic circuit die is combined with a memory circuit die in a single integrated circuit device capable of supporting memory intensive applications, such as 3D graphics rendering, encryption and signal processing.
Patent
Leads between chips assembly
TL;DR: In this article, a device and method for increasing integrated circuit density comprising at least a pair of superimposed dice, wherein at least one of the dice has at least 1 bond pad variably positioned on an active surface of the die, was presented.
Patent
Multi-chips semiconductor package and fabrication method
TL;DR: In this paper, a multi-chips semiconductor package and fabrication method mainly combines LOC and BGA techniques to overlap one chip upon another chip in an IC component package, where one chip uses leads of a lead frame as connection interface of the circuit in the chip to outside.
Patent
Thermal protection method for a power device
TL;DR: In this paper, a thermally protected power transistor comprising a first chip which included a power transistor and a second chip which includes protection circuitry is presented. But the first chip is mounted upside down on the power transistor chip, and the second chip has a plurality of metallic bumps formed thereon which are coupled to various portions of the protection circuitry, wherein at least one metallic bump serves as thermal couple.