Proceedings ArticleDOI
Communication based FPGA synthesis for multi-output Boolean functions
Christoph Scholl,Paul Molitor +1 more
- pp 43
TLDR
This work presents an efficient ROBDD based implementation of this common decomposition functions problem (CDF) using a minimal number r/sub k/ of single output Boolean decompositionfunction functions and results applying the method to FPGA synthesis are promising.Abstract:
One of the crucial problems multi level logic synthesis techniques for multi output Boolean functions f=(f/sub 1/,...,f/sub m/):{0,1}/sup n//spl rarr/{0,1}/sup m/ have to deal with is finding sublogic which can be shared by different outputs, i.e., finding Boolean functions /spl alpha/=(/spl alpha//sub 1/,...,/spl alpha//sub h/):{0,1}/sup p//spl rarr/{0,1}/sup h/ which can be used as common sublogic of good realizations of f/sub 1/,...,f/sub m/. We present an efficient ROBDD based implementation of this common decomposition functions problem (CDF). Formally, CDF is defined as follows: given m Boolean functions f/sub 1/,...,f/sub m/:{0,1}/sup n//spl rarr/{0,1}, and two natural numbers p and h, find h Boolean functions /spl alpha//sub 1/,..., /spl alpha//sub h/:{0, 1}/sup p//spl rarr/{0,1} such that /spl forall/1/spl les/k/spl les/m there is a decomposition of f/sub k/ of the form: f/sub k/(x/sub 1/,...x/sub n/)=g/sup (k)/(/spl alpha//sub 1/(x/sub 1/,...x/sub p/),...,/spl alpha//sub h/(x/sub 1/,...,x/sub p/),/spl alpha//sub h+1//sup (k)/(x/sub 1/,...,x/sub p/),...,/spl alpha/(r/sub k/)/sup (k)/(x/sub 1/,...x/sub p/),x/sub p+1/,...,x/sub n/) using a minimal number r/sub k/ of single output Boolean decomposition functions. Experimental results applying the method to FPGA synthesis are promising.read more
Citations
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On the decomposition of switching functions
TL;DR: In this article, the Ashenhurst chart method is generalized to non-junctive decompositions by means of the don't care conditions, which leads to designs of more economical switching circuits to realize the given switching function.
Journal ArticleDOI
BDD minimization using symmetries
TL;DR: This paper proves that using information about (partial) symmetries for the minimization of reduced ordered binary decision diagrams (ROBDD's) lead to improvements of the ROBDD sizes by up to 70%.
Proceedings ArticleDOI
Wireplanning in logic synthesis
TL;DR: A new logic synthesis methodology is proposed to deal with the increasing importance of the interconnect delay in deep submicron technologies to produce circuits which will have long paths even if placed optimally.
Journal Article
A Method to Decompose Multiple-Output Logic Functions
Tsutomu Sasao,Munehiro Matsuura +1 more
TL;DR: In this article, a method to decompose a given multiple-output circuit into two circuits with intermediate outputs is presented, where a BDD for characteristic function (BDD for CF) is used to represent a multiple-input-multiple-output function.
Proceedings ArticleDOI
Multi-output functional decomposition with exploitation of don't cares
TL;DR: This work presents a method for functional decomposition with a novel concept for the exploitation of don't cares thereby combining two essential goals: the minimization of the number of decomposition functions in the current decomposition step and the extraction of common subfunctions for multi-output Boolean functions.
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